An integrated circuit device includes: a substrate having an active surface, an inactive surface, a first region and a second region; a device structure on the active surface, and including individual devices disposed in the first region and a target through-region disposed in the second region; a multilayer wiring structure including wiring layers, wherein at least one wiring layer among the wiring layers has a landing pad overlapping the target through-region; and a through-via structure connected to the landing pad by penetrating through the second region and the target through-region, wherein the target through-region includes first insulating material patterns and dummy device patterns, wherein the first insulating material patterns each have a first area, wherein the dummy device patterns are on the active surface and each have a second area smaller than the first area, and wherein the first insulating material patterns are alternatively arranged with the dummy device patterns.

The present invention discloses a display panel and a head mounted device. The display panel includes a substrate and a plurality of micro light emitting units. A first position and a second position are defined at an edge and a center of the substrate respectively. The micro light emitting units are arranged and disposed on the substrate. Any two of the micro light emitting units are disposed at the first position and the second position respectively. Wherein each micro light emitting unit defines a luminating top surface, and a reference angle is defined between each luminating top surface and a reference plane respectively. Wherein the reference angle defined between each luminating top surface and the reference plane gradually decreases from the first position to the second position, and the luminating top surface of the micro light emitting unit located at the second position is parallel to the reference surface.

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure. The first front side interconnection layer is on a level higher than that of the conductive line.

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.

In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.

A package structure with a wettable side surface and a manufacturing method thereof, and a vertical package module are disclosed. The package structure includes a first dielectric layer, a chip and a circuit layer. The first dielectric layer is provided with a package cavity, side wall bonding pads are arranged on a side wall of the first dielectric layer and located outside the package cavity. The chip is packaged inside the package cavity, pins of the chip face first surface of the first dielectric layer. The circuit layer is arranged on the first surface of the first dielectric layer, and the circuit layer is directly or indirectly connected to the side wall bonding pads and the pins of the chip.

A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.