A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells, where X>Y.

A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.

A semiconductor structure includes a wafer having a wafer outer surface; a semiconductor chip; and a plurality of copper pillars on the semiconductor chip. The pillars have curved end portions and pillar outside surfaces. Also included are a plurality of copper pads on the wafer. The pads have end portions aligned with the curved end portions of the plurality of copper pillars on the semiconductor chip, and the curved end portions of the plurality of copper pillars and the end portions of the plurality of copper pads define a plurality of bonding material receiving regions. The pads have pad outside surfaces. A copper bonding layer is on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer. The portions have an annular shape about the copper pads when viewed in plan.

A manufacturing method for semiconductor packages is provided. Chips are provided on a carrier. Through interlayer vias are formed over the carrier to surround the chips. A molding compound is formed over the carrier to partially and laterally encapsulate the chip and the through interlayer vias. The molding compound comprises pits on a top surface thereof. A polymeric molding compound is formed on the molding compound to fill the pits of the molding compound.

In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein.

A semiconductor device comprises a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side, an electronic device on the substrate top side, and an encapsulant on the substrate top side and contacting a lateral surface of the electronic device. The substrate comprises a conductive structure and a dielectric structure that extends comprising a protrusion in contact with the encapsulant. The conductive structure comprises a lead comprising a lead flank, the lead flank comprising a cavity and a conductive coating on a surface of the lead in the cavity. The conductive structure comprises a pad exposed at the substrate top side, embedded in the dielectric structure, and adjacent to the protrusion, to electrically couple with the electronic device via a first internal interconnect. Other examples and related methods are also disclosed herein.