A semiconductor device comprises a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side, an electronic device on the substrate top side, and an encapsulant on the substrate top side and contacting a lateral surface of the electronic device. The substrate comprises a conductive structure and a dielectric structure that extends comprising a protrusion in contact with the encapsulant. The conductive structure comprises a lead comprising a lead flank, the lead flank comprising a cavity and a conductive coating on a surface of the lead in the cavity. The conductive structure comprises a pad exposed at the substrate top side, embedded in the dielectric structure, and adjacent to the protrusion, to electrically couple with the electronic device via a first internal interconnect. Other examples and related methods are also disclosed herein.

An apparatus includes a first substrate comprising one or more first interconnection layers, wherein a first die is coupled to a first side of the first substrate, and a second substrate comprising one or more second interconnection layers. The second die may be coupled to a first side of the second substrate, and a third die is coupled to a second side of the second substrate. The first substrate and the second substrate may be stacked together.

A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.

An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.