An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Chip structures and electronic modules including a power delivery network (PDN) routing structure and signal routing structure to balance power, signaling, and thermal requirements are described. In an embodiment, the chip includes a device layer, a PDN routing structure on top of the device layer, and a signal routing structure underneath the device layer.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.

A semiconductor package device is disclosed that includes a passive energy component integrated therein. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to the first surface. The semiconductor package device also includes a passive energy component positioned over the second surface. The passive energy component is electrically connected to one or more integrated circuits. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the passive energy component.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.

An embodiment semiconductor die may include a silicon substrate and a first through-silicon-via (TSV) formed in the silicon substrate, such that the first TSV includes a first protruding portion that protrudes from a surface of the silicon substrate. The embodiment semiconductor die may further include a dielectric isolation layer located between the surface of the silicon substrate and a plane parallel to a first contact surface of the first TSV such that the dielectric isolation layer laterally surrounds the first protruding portion of the first TSV without covering the first contact surface of the first TSV. The semiconductor die may include a redistribution layer including a first redistribution via that forms an electrical connection between the first contact surface of the first TSV and at least one redistribution interconnect. The dielectric isolation layer may prevent an electrically conducting pathway from forming between the first redistribution via and the silicon substrate.

This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer.