Disclosed are techniques for integrated circuits (ICs). In an aspect, an IC package includes a package substrate having an upper surface, a lower surface, a first side, and a second side perpendicular to the first side. The package substrate includes a metallization structure. The IC package further includes an IC die attached to the upper surface of the package substrate; first package bumps on the lower surface of the package substrate; and second package bumps on the lower surface of the package substrate. The first package bumps are arranged adjacent to one another along a diagonal direction that is diagonal to the package substrate, and the second package bumps are arranged adjacent to one another along the diagonal direction.

A display device includes a substrate including a conductive pad, a driving chip facing the substrate and including a conductive bump electrically connected to the conductive pad and an inspection bump which is insulated from the conductive pad, and an adhesive member which is between the conductive pad and the driving chip and connects the conductive pad to the driving chip. The adhesive member includes a first adhesive layer including a conductive ball, and a second adhesive layer facing the first adhesive layer, the second adhesive layer including a first area including a color-changing material, and a second area adjacent to the first area and excluding the color-changing material.

Connection terminals of a semiconductor module are disposed appropriately in accordance with the connection destination of the semiconductor module. A semiconductor module which includes at least one semiconductor element is mounted on a first surface of a main substrate, which has the first surface on which a first circuit element is mounted and a second surface on which a second circuit element is mounted. A plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate. The first connection terminal group is disposed on the outer peripheral side with respect to the second connection terminal group.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The seminconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

A semiconductor structure comprises: a substrate, an alignment mark, pillars, and a seal wall. The alignment mark is adjacent to a surface of the substrate. The pillars protrudes from the substrate. The seal wall protrudes from the surface of the substrate and surrounding the alignment mark. The seal wall is between the pillars and the alignment mark. The pillars is configured into at least two different groups with different average heights. The seal wall around the alignment mark can prevent the alignment mark from the coverage of the flux. Further, the seal wall can be formed with pillars at the same time, and the increased cost is limited.