A semiconductor chip may include: a body portion including a front surface and a back surface; penetrating electrodes penetrating the body portion; and back connection electrodes disposed over the back surface of the body portion and connected to the penetrating electrodes, wherein the penetrating electrodes include a power penetrating electrode for transmitting a power voltage and a ground penetrating electrode for transmitting a ground voltage, the back connection electrodes include a power back connection electrode connected to the power penetrating electrode and a ground back connection electrode connected to the ground penetrating electrode, and one power back connection electrode is connected with two or more power penetrating electrodes, and one ground back connection electrode is connected with two or more ground penetrating electrodes.

A radio frequency module includes: a first power amplifier and a second power amplifier on a first principal surface of a module board; external-connection terminals on a second principal surface; and a first via-conductor and a second via-conductor apart from each other inside of the board. One end of the first via-conductor is connected to a ground electrode of the first power amplifier, and the other end is connected to a first external-connection terminal. One end of the second via-conductor is connected to a ground electrode of the second power amplifier, and the other end is connected to a second external-connection terminal. The second via-conductor penetrates the board in a normal direction of the first principal surface, and the first via-conductor includes columnar conductors cascaded with central axes thereof displaced in the normal direction and has no region where the columnar conductors overlap in a plan view of the board.

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.

An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

A manufacturing method for an electronic component includes forming an electrically conductive pillar on a surface of a support, forming an intermediate layer covering a side surface of the pillar, forming a conductor layer covering a side surface of the intermediate layer, and molding a resin structure covering a side surface of the conductor layer.

A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.

A chip package includes a circuit board, a chip and an underfill. The circuit board includes a substrate, first circuit lines and second circuit lines. Each of the first circuit lines includes an inner lead and a first line fragment that are disposed on a chip mounting area and an underfill covering area of the substrate, respectively. The second circuit lines are disposed on the chip mounting area and not located between the adjacent inner leads so as to form a wider space between the adjacent first line fragments. The wider space enables the underfill to flow to between the circuit board and the chip and prevents air bubbles from being embedded in the underfill filled between the circuit board and the chip.

A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

The method of producing an electronic component (100) comprises a step A) of providing a semiconductor chip (2) having an underside (20), having a plurality of contact pins (21), and having at least one positioning pin (25) protruding from the underside. The contact pins are adapted to electrically contact the semiconductor chip. The positioning pin narrows in the direction away from the underside and protrudes further from the underside than the contact pins. The semiconductor chip is placed on the connection carrier, with the contact pins each being inserted into a contact recess and the positioning pin being inserted into the positioning recess. The contact pins are immersed in the molten solder material.

Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.