A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

An electronic apparatus and a circuit board thereof are provided. The electronic apparatus includes a control device that can operate with the circuit board, and includes a ball pad array. The ball pad array includes a plurality of power ball pads and a plurality of ground ball pads, which are arranged in the same pad arrangement region. At least a portion of the power ball pads and at least a portion of the ground ball pads are arranged in an alternate manner. The circuit board includes a solder pad array corresponding to the ball pad array of the control device so as to be disposed with the control device.

A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, a second sub-package, a first bridge die, and a second bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion of the second semiconductor chip is electrically connected to the first RDL pattern through the first bridge die. The second bridge die is disposed to electrically connect the second sub-package to the first semiconductor chip.

A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

A manufacturing method for an electronic component includes forming an electrically conductive pillar on a surface of a support, forming an intermediate layer covering a side surface of the pillar, forming a conductor layer covering a side surface of the intermediate layer, and molding a resin structure covering a side surface of the conductor layer.

Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

The present disclosure relates to evaluation of a mounted resistor formed between a bump and electrodes.

A display device of the present disclosure includes a display panel formed in a transparent substrate and a display driver driving the display panel. A plurality of bumps is formed on a connection surface of the display driver. A plurality of electrodes is formed on the transparent substrate and corresponds in position to the plurality of bumps. COG mounting enables the bumps on the display driver side to electrically connect to the electrodes on the transparent substrate side. On the connection surface of the display driver, the bumps, which are for use in signal transmission, further include a first evaluation-oriented bump (TA[i]) and a second evaluation-oriented bump (TB[i]). Evaluation-oriented electrodes (EL[i]) are disposed on the transparent substrate and correspond in position to the first evaluation-oriented bump (TA[i]) and the second evaluation-oriented bump (TB[i]). Upon completion of COG mounting, a resistance value evaluation circuit (140a) disposed on the display driver generates evaluation signal (DET[i]) corresponding to resistance value (RA[i]+RB[i]) between the evaluation-oriented electrodes and the first and second evaluation-oriented bumps.