A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

An electronic component embedded substrate includes a core structure including a first insulating body and core wiring layers and having a cavity and having a stopper layer disposed as a bottom surface; an electronic component disposed in the cavity and attached to the stopper layer; and a build-up structure including a second insulating body covering at least a portion each of the core structure and the electronic component and filling at least a portion of the cavity, and build-up wiring layers wherein the stopper layer has a first region in which a portion of one surface is exposed from the first insulating body and a second region in which the other portion of one surface is covered with the first insulating body, and a surface roughness of one surface of the stopper layer in the first region is greater than that of the stopper layer in the second region.

The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die. The first redistribution circuit structure is disposed on the device die and a first surface of the insulating encapsulant, and the first redistribution circuit structure is electrically connected to the device die.

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die. The first redistribution circuit structure is disposed on the device die structure and a first surface of the insulating encapsulant, and the first redistribution circuit structure is electrically connected to the device die structure.

A multichip module comprises a carrier, a plurality of chips, an electrical insulating layer, and an electrical interconnect structure. The carrier includes a bottom wall and four side walls defining an internal cavity. The chips are positioned in the internal cavity, with each chip including a plurality of bond pads. The electrical insulating layer is formed from electrically insulating material and is positioned on an upper surface of the carrier and the chips. The electrical interconnect structure includes a plurality of interconnect traces, with each interconnect trace formed from electrically conductive material and electrically connected to a first bond pad on a first chip and a second bond pad on a second chip. Each interconnect trace includes a bridge having a segment that is spaced apart from, and positioned above, the electrical insulating layer.