A display device includes a printed circuit board attached to a side of a substrate, a frame facing the printed circuit board, a cover layer disposed between the substrate and the frame and overlapping the printed circuit board in a plan view, and a first reflective layer disposed on a surface of the frame and disposed between the frame and the cover layer.

A display device includes: a substrate having an emission area and a non-emission area; a first bank in the non-emission area of the substrate and having an opening; electrodes on the first bank and spaced apart from each other; a second bank on the electrodes; and light emitting elements on the second bank between the electrodes. The second bank has a first area overlapping the light emitting elements and a second area in the opening in the first bank.

A display device includes a plurality of bank patterns disposed on a substrate and spaced apart from each other, a plurality of electrodes disposed on the substrate and extended parallel to each other and spaced apart from each other, an insulating layer disposed on the plurality of electrodes and the plurality of bank patterns, and a plurality of light emitting elements disposed on the insulating layer, having both ends disposed on the plurality of electrodes, wherein the plurality of bank patterns include sides facing each other, and portions of the plurality of light emitting elements are disposed on the sides of the plurality of bank patterns.

A method of producing an optoelectronic semiconductor chip includes in order: A) creating a nucleation layer on a growth substrate, B) applying a mask layer on to the nucleation layer, C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, E) growing a multiple quantum well structure on the coalescence layer, F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and G) detaching the growth substrate and creating a roughening by etching.

A method of manufacturing an electronic device is provided, wherein the method includes the following steps. A first substrate is provided, wherein the first substrate has a top surface and a side surface. A first wire is formed on the top surface of the first substrate. An auxiliary bonding pad is formed on the top surface of the first substrate, and the auxiliary bonding pad contacts the first wire. A second wire is formed on the side surface of the first substrate, and the second wire contacts the auxiliary bonding pad. The second wire and the auxiliary bonding pad include at least one same material.

Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

This disclosure relates to a new package concept that eliminates the need for epoxy or epoxy solder used in traditional clip/lead frame-based power packages. The disclosure overcomes this disadvantage in clip-based packages by depositing the interconnect structure directly to the bod pads. The formation of the interconnect done at lower temperature leads to lower stress induced onto the die. Another advantage of the present disclosure is that semiconductor dies packaged using a method according to the present disclosure will have smaller footprint as the pads are directly built up/deposited. Another advantage of the method according to the present disclosure is that it allows large scale, i.e., panel level processing. Such a panel may include multiple ICs, or transistor or any other semiconductor devices.

A display device includes a first display substrate including a light emitting element layer, a second display substrate facing the first display substrate and including a light blocking member and a color conversion layer, a coupling member that connects the first display substrate and the second display substrate to each other, and a filling member disposed between the first display substrate and the second display substrate. The filling member includes a photoinitiator that initiates by absorbing light of a wavelength band in a range of about 380 nm to about 500 nm, and the light blocking member and the color conversion layer cover a side of an entire surface of the second display substrate.

A display device includes a pixel circuit layer disposed on a substrate, a first electrode disposed on the pixel circuit layer, light emitting elements provided on the first electrode and electrically connected to the first electrode, a second electrode provided on the light emitting elements, and an insulating layer filling gaps between the light emitting elements between the first electrode and the second electrode. Each of the light emitting elements includes a first end and a second end, and the first end includes a curved surface.

A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.