In an embodiment, a package includes a first package structure including a first integrated circuit die having an active side and a back-side, the active side including die connectors, a second integrated circuit die adjacent the first integrated circuit die, the second integrated circuit die having an active side and a back-side, the active side including die connectors, a routing die including die connectors bonded to the active sides of the first integrated circuit die and the second integrated circuit die, the routing die electrically coupling the first integrated circuit die to the second integrated circuit die, an encapsulant encapsulating the first integrated circuit die, the second integrated circuit die, and the routing die, and a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the second integrated circuit die.

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

A semiconductor apparatus includes three or more semiconductor devices connected in parallel with each other and an interconnect substrate arranged on the semiconductor devices, wherein the semiconductor devices have respective control electrodes and are switched by a voltage applied to the control electrodes, wherein the interconnect substrate includes an insulating layer and a first interconnect pattern arranged on an opposite side of the insulating layer from the semiconductor devices and connecting the control electrodes of the semiconductor devices, wherein the first interconnect pattern includes a same number of interconnects of equal length as the semiconductor devices, and a voltage input point configured to receive a voltage applied to the control electrodes via the interconnects of equal length, and wherein the control electrodes of the semiconductor devices are connected to the voltage input point only by the interconnects of equal length, which extend in different directions from the voltage input point.

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

A first die includes a first substrate and a first interconnect structure. A second die is bonded to the first die and includes a second substrate and a second interconnect structure, such that the first and second interconnect structures are arranged between the first and second substrates. A redistribution layer (RDL) stack is arranged on an outer side of the first die opposite the first interconnect structure. A heat path includes a through substrate via (TSV) extending from a conductive layer in the first interconnect structure, through the first substrate, and into the RDL stack. An RDL dielectric material is included in the RDL stack and separates the heat path from an ambient environment. A thermal conductivity of the RDL dielectric is over twenty times a thermal conductivity of an interconnect dielectric material of the first interconnect structure or of the second interconnect structure.

Some embodiments relate to a method of forming a redistribution layer (RDL) stack of a 3D integrated circuit stack. The method comprises removing a substrate form the first side of a first die to expose a first dielectric layer. A spiral trench is formed in the first dielectric layer with one end of the spiral trench directly over a through silicon via (TSV) beneath the first dielectric layer. A first barrier layer is formed along sidewalls of the spiral trench, the first barrier layer being thermally coupled to the TSV. A first conductive wire is formed within the spiral trench, separated from the first dielectric layer by the barrier layer.