Patent classifications
H01L2224/37005
Engineered Interconnect Structures for Enhanced Bonding Strength
Interconnect structures for power semiconductor device packages are provided. In one example, a power semiconductor device package may include one or more semiconductor die, a submount, and at least one interconnect structure. The one or more wide bandgap semiconductor die may be on the submount. The at least one interconnect structure may include at least one texturized surface.
Connecting strip for discrete and power electronic devices
A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.
METAL CONNECTOR IN SEMICONDUCTOR DEVICE PACKAGE
A connector for a semiconductor device package. The connector may include a middle portion, having a curved concave shape in a front view, with respect to a given surface. The connector may include a first contacting portion, integrally connected to the middle portion on a first side, as wells as a second contacting portion, integrally connected to the middle portion on a second side, wherein the first contacting portion and the second contacting portion define a curved convex surface in the front view. with respect to the given surface. In some implementations, the connector may include a slot assembly as well as one or more indents that define a meander path, which structure imparts a greater elastic flexibility, such as under mechanical load.
LEADFRAME AND ELECTRONIC DEVICE SINGULATION PROCESS
An electronic device and method are provided. The method includes providing an array of electronic devices having leadframes where the leadframes include at least one depopulated lead and external leads interconnected by a first dambar, a second dambar, and a connection assembly. The connection assembly connects the first dambar to a first external lead of a first leadframe and to a second external lead of a second adjacent leadframe. A first punch process is performed to remove the first dambar and the second dambar from the leadframes. A second punch process is performed to create a cut in the connection assembly proximate the first external lead adjacent to the at least one depopulated lead to disconnect the connection assembly from the first external lead. A trimming process is performed to trim external leads of the leadframes to their required length while simultaneously removing the connection assembly.
CONNECTING STRIP FOR DISCRETE AND POWER ELECTRONIC DEVICES
A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.
Multi-chip device with gate redistribution structure
A power device package includes first and second power transistor chips each having a control electrode, a first load electrode and a second load electrode. A control package terminal is electrically coupled to the control electrode of the first power transistor chip via a first wire bond connection and to the control electrode of the second power transistor chip via a second wire bond connection. A first package terminal is electrically coupled to the first load electrode of the first and second power transistor chips. A second package terminal is electrically coupled to the second load electrode of the first power transistor chip and/or the second power transistor chip. A length of the first wire bond connection is greater than a length of the second wire bond connection, and a cross-sectional area of the first wire bond connection is greater than a cross-sectional area of the second wire bond connection.
SEMICONDUCTOR DEVICE HAVING A WIRING MEMBER WITH AN UNEVEN BONDING SURFACE
A semiconductor device, including: a semiconductor chip having a first electrode and a second electrode respectively on a upper surface and a lower surface thereof; and a wiring member including a bonding portion having a bonding surface, which is bonded to the first electrode with a solder therebetween, and a rising portion extending from an outer periphery of the bonding portion, the bonding surface being located, in a plan view of the semiconductor device, within the upper surface of the semiconductor chip. The bonding surface has an outer edge area and a middle area. In a height direction of the semiconductor device, a first height from the outer edge area of the bonding surface to the upper surface of the semiconductor chip is greater than a second height from the middle area of the bonding surface to the upper surface of the semiconductor chip.
Semiconductor device
A semiconductor device includes: a first connector including a first plate having a first upper surface and a first terminal connected to the first plate, a first plate including a second plate and a third plate, a plate thickness of the second plate being thinner than a plate thickness of the third plate, the third plate being provided between the second plate and the first terminal; a semiconductor chip provided on the first upper surface; a first bonding material provided between the first upper surface and the semiconductor chip; a second connector provided on the semiconductor chip, a third connector, the first plate being provided between the first terminal and the third connector; a second bonding material provided between the second connector and the semiconductor chip; and a third bonding material provided between the second connector and the third connector.