An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

A semiconductor device package includes a conductive clip that has a recess and that is configured to mount to a substrate along a first surface and a second surface that bound the recess, and that includes at least two vertical channel transistors that are of a same type and that are mounted within the recess in a same orientation such that a drain or source contact is coupled to the conductive clip, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip.

A semiconductor device package includes a conductive clip that has a recess and that is configured to mount to a substrate along a first surface and a second surface that bound the recess, and that includes at least two vertical channel transistors that are of a same type and that are mounted within the recess in a same orientation such that a drain or source contact is coupled to the conductive clip, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip.

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

The invention relates to a chip arrangement (10) and to a method for forming a contact connection (11) between a chip (18), in particular a power transistor or the like, and a conductor material track (14), the conductor material track being formed on a non-conductive substrate (12), the chip being arranged on the substrate or on a conductor material track (15), a silver paste (29) or a copper paste being applied to each of a chip contact surface (25) of the chip and the conductor material track (28), a contact conductor (30) being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being at least partially vaporized by heating and the contact connection being formed by sintering the silver paste or the copper paste by means of laser energy.

To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip FET and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed.

To provide a semiconductor module capable of shortening of the manufacturing tact time, reducing the manufacturing costs, and improving assembility. A semiconductor module (30) includes substrate (31) made of metal, an insulating layer (32) formed on the substrate (31), a plurality of wiring patterns (33a to 33d) formed on the insulating layer (32), a bare-chip transistor (35) mounted on a wiring pattern (33a) via a solder (34a); and a metal plate connector (36a, 36b) jointing an electrode (S, G) of the bare-chip transistor (35) and a wiring pattern (33b, 33c) via a solder (34b, 34c). The metal plate connector (36a, 36b) has a bridge shape, and has a flat surface and a center of gravity at a middle portion of the component.