H01L2224/45005

Bonding wire for semiconductor device

A bonding wire for a semiconductor device including a coating layer having Pd as a main component on the surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing a metallic element of Group 10 of the Periodic Table of Elements in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in 2nd bondability and excellent ball bondability in a high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

Electronic device and method for production

An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 m provides a strength ratio of 1.6 or less.

BONDING WIRE FOR SEMICONDUCTOR DEVICE
20170200690 · 2017-07-13 ·

There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir, and Pt. A concentration of the elements in total relative to the entire wire is 0.03% by mass or more and 2% by mass or less. When measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 50% or more among crystal orientations in the wire axis direction. An average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 m or more and 1.3 m or less.

BONDING WIRE FOR SEMICONDUCTOR DEVICE
20170179064 · 2017-06-22 ·

A bonding wire for a semiconductor device including a coating layer having Pd as a main component on the surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing a metallic element of Group 10 of the Periodic Table of Elements in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in 2nd bondability and excellent ball bondability in a high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

PILLAR STRUCTURE AND MANUFACTURING METHOD THEREOF
20170110431 · 2017-04-20 ·

A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.

MOLDED POWER DIE PACKAGE WITH VERTICAL INTERCONNECT

A power die package includes a power die having a plurality of bond pads at an upper surface of the power die. The package further includes a plurality of contact structures. A contact structure includes: a bond wire bonded to one of the plurality of bond pads and folded back to the bond pad to form a closed loop, or at least three bumps laterally spaced from one another and disposed on one or more bond pads; and a continuous longitudinally extended electrically conductive element connected to the at least three bumps in at least three contact positions. The conductive element bends away from the power die between pairs of consecutive contact positions. The package further includes a mold compound partially encapsulating the contact structure. The mold compound includes an outer surface facing away from the power die. The contact structure is partially exposed at the outer surface.

PANEL LEVEL FABRICATION OF STACKED ELECTRONIC DEVICE PACKAGES WITH ENCLOSED CAVITIES

Electronic device packages that include one or more circuit substrates, one or more cavities defined by a cover separated from a circuit substrate by an interposer substrate with an aperture disposed above the circuit substrate can be formed by panel-level fabrication processes in which multiple assemblies are formed by singulating a larger panel assembly formed by multiples panels bonded to each other. A panel that includes multiple levels is partially diced to form channels which are filled with molding material. The subsequent structure is diced again to singulate individual stacked packages that include a portion of the molding material surrounding one or more interposers. The molding material can seal gaps between an interposer and a circuit substrate to which it is bonded, as well as providing electrical isolation between electrical interconnects that would otherwise be exposed at edges of each package.

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME, AND POWER CONVERSION APPARATUS
20250192098 · 2025-06-12 · ·

A semiconductor apparatus includes a semiconductor device, a lower wire member, and an upper wire member. The semiconductor device includes a semiconductor device body having a main surface, and a metal layer. The lower wire member includes an end surface and an end surface. In a plan view of the main surface, the end surface and the end surface are located inside a periphery of the semiconductor device. The upper wire member is stacked on the lower wire member. In the plan view of the main surface, a portion of the upper wire member is located outside the periphery of the semiconductor device. The upper wire member is joined to the metal layer with the lower wire member being interposed therebetween.