A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

In at least one embodiment, the power semiconductor device (1) comprises: at least one support (2), at least one power semiconductor chip (24) is arranged on a support top side (20), a heat sink (3) having a heat sink top side (30), the at least one support (2) is arranged on the heat sink top side (30), and a mold body (4) of an electric insulating material in direct contact with the at least one support (2) and the heat sink (3),
wherein the mold body (4) fixes and presses the at least one support (2) onto the heat sink (3).

A method of manufacturing a pre-mold substrate includes preparing an electrically conductive substrate, forming a groove on one surface of the substrate, arranging a resin to cover one surface of the substrate and the groove, removing a portion of the resin so that at least a portion of one surface of the substrate protrudes higher than a surface of the resin covering the groove, and forming a circuit pattern on another surface of the substrate.

A wiring body disposed above a substrate including a conductor includes: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. The material or structure of a lower layer in the via electrode and the material or structure of a lower layer in the wiring are different.

A method of interconnecting components of a semiconductor device using wire bonding is presented. The method includes creating a free air ball at a first end of an aluminum wire that has a coating surrounding the aluminum wire, wherein the coating comprises palladium, and wherein the free air ball is substantially free of the coating. The method further includes the step of bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the resultant ball bond and the bond pad form a substantially homogenous, aluminum-to-aluminum bond. The method may further include bonding a second, opposing end of the coated-aluminum wire to a bond site separate from the semiconductor chip, the bond site having a palladium surface layer, wherein the second end of the coated-aluminum wire and the bond site form a substantially homogenous, palladium-to-palladium bond.

A method of interconnecting components of a semiconductor device using wire bonding is presented. The method includes creating a free air ball at a first end of an aluminum wire that has a coating surrounding the aluminum wire, wherein the coating comprises palladium, and wherein the free air ball is substantially free of the coating. The method further includes the step of bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the resultant ball bond and the bond pad form a substantially homogenous, aluminum-to-aluminum bond. The method may further include bonding a second, opposing end of the coated-aluminum wire to a bond site separate from the semiconductor chip, the bond site having a palladium surface layer, wherein the second end of the coated-aluminum wire and the bond site form a substantially homogenous, palladium-to-palladium bond.

A power semiconductor device includes a semiconductor substrate. A signal routing structure is disposed above the semiconductor substrate. The signal routing structure comprises a specific metal. A solderable power pad forms a power terminal of the power semiconductor device. The solderable power pad comprises the specific metal. An electrically insulating dielectric passivation layer is disposed between the solderable power pad and the signal routing structure.

The present disclosure relates to semiconductors technologies and provides a chip package and a manufacturing method of the chip package. The chip package includes: an interposer; a plurality of semiconductor chips optically connected to the interposer, wherein the plurality of semiconductor chips includes at least four semiconductor chips; and an optical interconnect chip optically connected to the interpose. Each of the plurality of semiconductor chips is configured to be optically connected to the optical interconnect chip via the interposer, to realize optical signal communication between any two of the plurality of semiconductor chips.

A method of manufacturing a bond pad structure may include depositing an aluminum-copper (AlCu) layer over a dielectric layer; and depositing an aluminum-chromium (AlCr) layer directly over the AlCu layer.

A memory device includes a circuit having an element on a substrate, an interconnection layer above the circuit and that includes a pad electrode having a region for metal wiring bonding, a plurality of electrode layers between the circuit and the interconnection layer and that are stacked in a first direction from the circuit to the interconnection layer, a semiconductor pillar that extends in the first direction, and a storage film between the electrode layers and the semiconductor pillar. The pad electrode overlaps the circuit element as viewed in the first direction.