A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component.

A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component.

A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

A rectangular power module with a body having two short ends defining a length and two long sides defining a width having three parallel circuit paths crossing the short width distance from side to side using side positioned gate terminals and planar top positioned top power terminal positioned between MOSFETS in the circuit for even thermal positioning and reduced current path, inductance, and resistance and increased power density.

A rectangular power module with a body having two short ends defining a length and two long sides defining a width having three parallel circuit paths crossing the short width distance from side to side using side positioned gate terminals and planar top positioned top power terminal positioned between MOSFETS in the circuit for even thermal positioning and reduced current path, inductance, and resistance and increased power density.

A semiconductor device includes a multi-layer board which a wiring pattern and a grounding pattern are formed. A plurality of semiconductor elements are mounted on the multi-layer board. An insulating sealing member is provided on the multi-layer board and is covering the plurality of semiconductor elements. A metal film is provided on the insulating sealing member. An in-groove metal is provided in contact with a plurality of grooves extending from a side-surface upper end of the insulating sealing member to a side-surface lower end of the multi-layer board. An in-hole metal is provided in an inner wall of a hole penetrating through the insulating sealing member and is extending to the multi-layer board. The in-hole metal is contacting with the metal film and the grounding pattern.

A semiconductor device includes a multi-layer board which a wiring pattern and a grounding pattern are formed. A plurality of semiconductor elements are mounted on the multi-layer board. An insulating sealing member is provided on the multi-layer board and is covering the plurality of semiconductor elements. A metal film is provided on the insulating sealing member. An in-groove metal is provided in contact with a plurality of grooves extending from a side-surface upper end of the insulating sealing member to a side-surface lower end of the multi-layer board. An in-hole metal is provided in an inner wall of a hole penetrating through the insulating sealing member and is extending to the multi-layer board. The in-hole metal is contacting with the metal film and the grounding pattern.

A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.

A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.