A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.

A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.

A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

A semiconductor device includes an electronic component that includes an oscillator and has terminals on one face. A semiconductor chip is electrically connected to the electronic component and also includes terminals on one face thereof. The electronic component and the semiconductor chip are mounted to a mounting base such that the terminals of the electronic component and the terminals of the semiconductor chip face in the same direction. First bonding wires are connected to the terminals of the semiconductor chip, and second bonding wires having an apex height smaller than that of the first bonding wires connect the terminals of the electronic component to the terminals of the semiconductor chip. A sealing member completely seals within at least the electronic component.

A semiconductor device includes an electronic component that includes an oscillator and has terminals on one face. A semiconductor chip is electrically connected to the electronic component and also includes terminals on one face thereof. The electronic component and the semiconductor chip are mounted to a mounting base such that the terminals of the electronic component and the terminals of the semiconductor chip face in the same direction. First bonding wires are connected to the terminals of the semiconductor chip, and second bonding wires having an apex height smaller than that of the first bonding wires connect the terminals of the electronic component to the terminals of the semiconductor chip. A sealing member completely seals within at least the electronic component.

A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED structures are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED structures. Each of the LED structures includes a first electrode and a second electrode. Light emitted from at least one of the LED structures passes through the transparent substrate and emerges from the second main surface. An illumination device includes the semiconductor light emitting element and a supporting base. The semiconductor light emitting element is disposed on the supporting base, and an angle is formed between the semiconductor light emitting element and the supporting base.

A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED structures are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED structures. Each of the LED structures includes a first electrode and a second electrode. Light emitted from at least one of the LED structures passes through the transparent substrate and emerges from the second main surface. An illumination device includes the semiconductor light emitting element and a supporting base. The semiconductor light emitting element is disposed on the supporting base, and an angle is formed between the semiconductor light emitting element and the supporting base.