H01L2224/45565

SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE
20220052003 · 2022-02-17 ·

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

SEMICONDUCTOR DEVICE
20170278771 · 2017-09-28 · ·

A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some implementations, the semiconductor device includes: a laminated substrate on which a semiconductor element is mounted; and a sealing material. In some implementations, the sealing material contains an epoxy base resin, a curing agent, and a phosphonic acid.

SEMICONDUCTOR DEVICE
20170278771 · 2017-09-28 · ·

A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some implementations, the semiconductor device includes: a laminated substrate on which a semiconductor element is mounted; and a sealing material. In some implementations, the sealing material contains an epoxy base resin, a curing agent, and a phosphonic acid.

MULTICHIP PACKAGE AND FABRICATION METHOD THEREOF
20220310495 · 2022-09-29 · ·

A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

MULTICHIP PACKAGE AND FABRICATION METHOD THEREOF
20220310495 · 2022-09-29 · ·

A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

Multiple bond via arrays of different wire heights on a same substrate
09728527 · 2017-08-08 · ·

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Multiple bond via arrays of different wire heights on a same substrate
09728527 · 2017-08-08 · ·

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Coated wire

A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core itself consists of: (a) pure silver consisting of (a1) silver in an amount in the range of from 99.99 to 100 wt.-% and (a2) further components in a total amount of from 0 to 100 wt.-ppm or (b) doped silver consisting of (b1) silver in an amount in the range of from >99.49 to 99.997 wt.-%, (b2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm and (b3) further components in a total amount of from 0 to 100 wt.-ppm, or (c) a silver alloy consisting of (c1) silver in an amount in the range of from 89.99 to 99.5 wt.-%, (c2) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (c3) further components in a total amount of from 0 to 100 wt.-ppm, or (d) a doped silver alloy consisting of (d1) silver in an amount in the range of from >89.49 to 99.497 wt.-%, (d2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm, (d3) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (d4) further components in a total amount of from 0 to 100 wt.-ppm, wherein the at least one doping element (d2) is other than the at least one alloying element (d3), wherein the individual amount of any further component is less than 30 wt.-ppm, wherein the individual amount of any doping element is at least 30 wt.-ppm, wherein all amounts in wt.-% and wt.-ppm are based on the total weight of the core, and wherein the coating layer is a double-layer comprised of a 1 to 1000 nm inner layer of gold and an adjacent 0.5 to 100 nm thick outer layer of palladium or a double-layer comprised of a 0.5 to 100 nm thick inner layer of palladium and an adjacent >200 to 1000 nm thick outer layer of gold.

A NOVEL LED SUPPORT STRUCTURE
20170271560 · 2017-09-21 ·

The invention discloses a novel LED support structure, including a metal support terminal; an LED chip fixed on the metal support terminal; a bonding wire for connecting the surface of the metal support terminal with the LED chip; and a packaging adhesive for protecting the LED chip. The invention further includes a plastic material covered on the surface of the metal support terminal; and a plastic material reflector cup for coating the metal support terminal. The metal support terminal includes a metal pin embedded in the plastic material reflector cup and a metal tube pin disposed outside the plastic material reflector cup, wherein the metal pin is provided with a functional zone and a non-functional zone.

A NOVEL LED SUPPORT STRUCTURE
20170271560 · 2017-09-21 ·

The invention discloses a novel LED support structure, including a metal support terminal; an LED chip fixed on the metal support terminal; a bonding wire for connecting the surface of the metal support terminal with the LED chip; and a packaging adhesive for protecting the LED chip. The invention further includes a plastic material covered on the surface of the metal support terminal; and a plastic material reflector cup for coating the metal support terminal. The metal support terminal includes a metal pin embedded in the plastic material reflector cup and a metal tube pin disposed outside the plastic material reflector cup, wherein the metal pin is provided with a functional zone and a non-functional zone.