Provided is a semiconductor package including a first wiring structure including a plurality of first wiring patterns respectively including a plurality of first lower surface connection pads and a plurality of first upper surface connection pads, a second wiring structure including a plurality of second wiring patterns respectively including a plurality of second lower surface connection pads and a plurality of second upper surface connection pads, a semiconductor chip arranged between the first wiring structure and the second wiring structure, a plurality of connection structures connecting some of the plurality of first upper surface connection pads to the plurality of second lower surface connection pads, and arranged adjacent to the semiconductor chip, and a binding reinforcement layer on side surfaces of each of the plurality of connection structures and at least a portion of the semiconductor chip.

To improve an integration degree of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode. Part of the external pad electrode is located in a region outside the rewiring.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

A semiconductor package may include an interconnection structure in which at least one insulating layer and at least one interconnection layer are alternately stacked, a semiconductor chip including a plurality of pads, the semiconductor chip at least partially overlapping with the interconnection structure in the vertical direction, a plurality of bumps between the plurality of pads and the interconnection structure, a peripheral pad portion at least a portion of which on a side surface of the semiconductor chip and electrically connected to the semiconductor chip by a surface thereof that opposing the semiconductor chip, and a peripheral connection portion electrically connecting the peripheral pad portion and the interconnection structure to each other.

This wire bonding apparatus has a capillary, a movement mechanism moving the capillary, and a control unit controlling driving of the movement mechanism. The control unit at least causes execution of: a first process (trajectory a) of lowering the capillary, after a FAB is formed, to pressure bonding height at a first bonding point to form a pressure bonded ball and a column part at the first bonding point; a second process (trajectory b) of moving the capillary horizontally at the pressure bonding height after execution of the first process to scarp off the column part by the capillary; and a third process (trajectory c-k) of repeating a pressing operation at least once after execution of the second process, the pressing operation involving moving the capillary forward and lowering the capillary temporarily during movement so that the capillary presses down on a wire portion positioned over the pressure bonded ball.

A method of manufacturing an IC device includes forming first through fourth metal segments extending in a first direction in a first metal layer, the third and fourth metal segments having a width greater than a width of the first and second metal segments, the third metal segment separated from the first or second metal segment by a first distance, and the third and fourth metal segments separated from each other by a second distance greater than the first distance, forming fifth and sixth metal segments extending in a second direction perpendicular to the first direction in second and third metal layers and configured to electrically connect the first and second metal segments to each other and electrically connect the third and fourth metal segments to each other. The first, second, and fifth metal segments are electrically isolated from the third, fourth, and sixth metal segments.

A semiconductor package includes a redistribution structure including redistribution vias extending from redistribution layers into an insulating layer, a plurality of semiconductor chips stacked on the redistribution structure, a molded layer between the redistribution structure and the plurality of semiconductor chips, connection wires electrically connecting corresponding connection pads and redistribution vias, and connection bumps below the redistribution structure. The connection wires include a first portion extending from each of the connection pads at a first inclination angle for a bottom surface of the molded layer, and a second portion extending from the first portion at a second inclination angle, narrower than the first inclination angle for the bottom surface of the molded layer. The second portion has an end surface in contact with corresponding redistribution vias, and each of the redistribution vias has a top surface in contact with the end surface of the second portion.