Light emission efficiency is increased in an eye-safe light source by regulating light distribution properties. An eye-safe light source includes a package, a semiconductor laser that emits laser light from a left light emission end surface and a right light emission end surface, and a wire that is joined to the semiconductor laser. The semiconductor laser is joined to the package such that the laser light is emitted parallel to an upper surface of a lead frame of the package. The package includes reflection surfaces that face the left light emission end surface and the right light emission end surface and reflect the laser light. In top view, a direction in which the wire extends is perpendicular to a direction of emission of the laser light.

A semiconductor package including a substrate including an external terminal; a first semiconductor chip on the substrate and having a first and a second region; at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and at least one third semiconductor chip on the at least one second semiconductor chip, wherein the first semiconductor chip includes a first pad electrically connected to the at least one second semiconductor chip; a second pad electrically connected to the at least one third semiconductor chip; and a third pad electrically connected to the external terminal, the first pad is on the top surface of the first region, and at least one of the second pad and the third pad is on a top surface of the second region.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

Embodiments disclosed herein include wire bonds and tools for forming wire bonds. In an embodiment, a wire bond may comprise a first attachment ball, and a first wire having a first portion contacting the first attachment ball and a second portion. In an embodiment, the wire bond may further comprise a second attachment ball, and a second wire having a first portion contacting the second attachment ball and a second portion. In an embodiment, the second portion of the first wire is connected to the second portion of the second wire.

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.

A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

The present disclosure is drawn to wirebonding for optical engines having side-mounted optoelectronic components. An integrated circuit is mounted on a first surface of a substrate block, and an optoelectronic component is positioned on a second surface of the substrate block and is oriented to emit light in a direction parallel to a plane defined by the first surface. A wirebond is drawn between the integrated circuit and a base substrate on which the substrate block is mounted. A optoelectronic component is then contacted with the wirebond, and a portion of the wirebond between the optoelectronic component and the base substrate is removed.