A chip assembly having a carrier having a cavity and at least one carrier contact, a chip arranged in the cavity and having at least one chip contact, and a wirebond wire, which electrically conductively connects the at least one chip contact to the at least one carrier contact, wherein the wirebond wire is flat-pressed in at least one subregion.

A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on or above the carrier, an electrically insulating and thermally conductive layer on at least part of an upper main surface of the electronic component, and a metal block on the electrically insulating and thermally conductive layer. An encapsulant at least partially encapsulates the electronic component, the carrier, the electrically insulating and thermally conductive layer and the metal block so that an upper main surface of the metal block is exposed beyond the encapsulant.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

A semiconductor package according to the exemplary embodiments of the disclosure includes a base substrate including a base bonding pad, a first semiconductor chip disposed on the base substrate, a first adhesive layer provided under the first semiconductor chip, a first bonding pad provided in a bonding region on an upper surface of the first semiconductor chip, a first bonding wire interconnecting the base bonding pad and the first bonding pad, and a crack preventer provided in a first region at the upper surface of the first semiconductor chip. The crack preventer includes dummy pads provided at opposite sides of the first region and a dummy wire interconnecting the dummy pads.

A package structure includes a leadframe, at least two dies, at least one spacer and a plastic package material. The leadframe includes a die pad. The dies are disposed on the die pad of the leadframe. The spacer is disposed between at least one of the dies and the die pad. The plastic package material is disposed on the leadframe, and covers the dies. A first minimum spacing distance is between one of a plurality of edges of the spacer and one of a plurality of edges of the die pad, a second minimum spacing distance is between one of a plurality of edges of the dies and one of the edges of the die pad, and the first minimum spacing distance is larger than the second minimum spacing distance.

An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands.

An object is to provide a technology that reduces the number of components and that is capable of suppressing the cost. A structure including semiconductor elements, a plurality of electrode terminals, and a dam bar for connecting the plurality of electrode terminals is prepared, and a part of the structure including a part of the plurality of electrode terminals and the dam bar is arranged in the terminal hole. Further, the part of the structure is clamped by a movable clamp inside the terminal hole, and at least a portion of the movable clamp is fitted into the terminal hole, and then a resin is injected into an internal space of a pair of molds.

A measuring device includes two sensor chips that measure a flow rate of a fluid flowing through a pipe, electrode pads extending from a temperature measuring section and from a heater, respectively, toward peripheries of the two sensor chips, and wires that are electrically connected to the electrode pads and via which a measurement signal that is output from the temperature measuring section or the heater is transmitted to outside of the sensor chips. Each of the electrode pads includes a straight portion that extends linearly from the temperature measuring section or the heater and a wide portion that is formed at a leading end of each of the electrode pads and is wider than the straight portion, and an entire surface area of the wide portion is set as a wire-bonding-allowed region, to which one of the wires is to be bonded.

A switched-mode power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases, comprising at least one block of two converter arms, wherein a half-arm of a converter arm comprises: a first set of P2 switches in series; a second set of P2 switches in series; and a third set of diodes, arranged between the first set and the second set, comprising M2 subsets in series, indexed i[[1; M]], respectively comprising N.sub.i2 diodes in parallel.

An electronic device includes a carrier and a semiconductor chip, wherein the carrier includes a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier includes a solder terminal for electrical contacting arranged on the second dielectric layer.