A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

A semiconductor package includes a metal flange having a lower surface and an upper surface opposite the lower surface. An electrically insulating window frame is disposed on the upper surface of the flange. The electrically insulating window frame forms a ring around a periphery of the metal flange so as to expose the upper surface of the metal flange in a central die attach region. A first electrically conductive lead is disposed on the electrically insulating window frame and extends away from a first side of the metal flange. A second electrically conductive lead is disposed on the electrically insulating window frame and extends away from a second side of the metal flange, the second side being opposite the first side. A first harmonic filtering feature is formed on a portion of the electrically insulating window frame and is electrically connected to the first electrically conductive lead.

A semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, a plurality of lead portions, and a sealing portion sealing them. The sealing portion has a first main surface and a second main surface opposite the first main surface. A groove portion is formed in the sealing portion at the first main surface. At the first main surface of the sealing portion, each of the first chip mounting portion and the second chip mounting portion is exposed from the sealing portion. At the first main surface of the sealing portion, the groove portion is formed between an exposed portion of the first chip mounting portion and an exposed portion of the second chip mounting portion.

A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically coupling the sensor chip to the substrate, a supporting colloid layer disposed on the substrate, and a light-permeable sheet that is disposed on the supporting colloid layer. The substrate has a first board surface and a second board surface that is opposite to the first board surface. The substrate has a chip-accommodating slot recessed in the first board surface. The sensor chip is disposed in the chip-accommodating slot, and a gap distance between a top surface of the sensor chip and the first board surface is less than or equal to 10 ?m. The supporting colloid layer is ring-shaped and is disposed on the first board surface, and each of the wires is at least partially embedded in the supporting colloid layer.

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

An electronic device made from the method of providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, laser bending the shaped metallic interconnects; and transferring the shaped metallic interconnects onto a receiving substrate or device.

A semiconductor apparatus includes a first semiconductor element, a second semiconductor element, and a metal pattern formed on the second semiconductor clement. The metal pattern includes a first connection connected to the first semiconductor element and a second connection connected to a first terminal portion of the first semiconductor element and positioned away from the first connection. A first electrically conductive path formed between the first and second connections has a larger electric resistance than an electric resistance of a second electrically conductive path formed between the second connection and the first terminal portion.

Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. As viewed in a plane, the leads LD9 intersect with a side MRd4 of the sealing portion and the leads LD10 intersect with a side MRd2 of the sealing portion.

It is an object of the present invention to improve a heat radiation property of a metal wire on a semiconductor chip in a power module. A power module includes: a plurality of metal wires connected to a surface of at least one semiconductor chip; and a thermal conductive sheet having contact with the metal wire. The metal wire includes: at least one first metal wire connecting a surface of the semiconductor chip and a circuit pattern and at least one second metal wire connecting two points on the surface of the semiconductor chip and having the same potential as the first metal wire. The thermal conductive sheet includes a graphite sheet, and a sheet surface of the thermal conductive sheet has contact with the at least one first metal wire and the at least one second metal wire.