A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device.

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

A semiconductor package with a leadframe to mount a transistor device prevents malfunction. The semiconductor package includes a leadframe including at least one or more transistor die attach pads where a first transistor device and a second transistor device are arranged, a driver die attach pad where a driver semiconductor chip is arranged, a first driver lead electrically connected to the driver semiconductor chip, and a second driver lead arranged between the first driver lead and the at least one or more transistor die attach pads, a chip bonding wire electrically connecting the first transistor device with the driver semiconductor chip, a first transistor bonding wire electrically connecting the first driver lead with the second transistor device, and a first insulator arranged on the second driver lead to insulate the second driver lead and the first transistor bonding wire from each other.

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.

A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the semiconductor chip. The leadframe includes a terminal having a pillar shape. The terminal includes a first end surface, a second end surface facing away from the first end surface, and a side surface extending vertically between the first end surface and the second end surface. The side surface is stepped to form a step surface facing away from the second end surface and having an uneven surface part formed therein. A first portion of the terminal extending from the first end surface toward the second end surface and including the step surface is covered with the encapsulation resin. A second portion of the terminal extending from the first portion to the second end surface projects from the encapsulation resin.

This invention is provided with: a circuit board which is placed in a package and in which an electric circuit including a power semiconductor element is formed; and a plurality of press-fit terminals each having a wire-bond portion electrically connected in the package to the electric circuit, a press-fit portion for making electrical connection with an apparatus to be connected, and a body portion whose one end portion continuous to the wire bond portion is internally fastened to the package and whose other end portion supports the press-fit portion so as to place the press-fit portion away from the package; wherein in each of the plurality of press-fit terminals, at a portion in the body portion exposed from the package, there is formed a constriction portion that is constricted from both sides in a direction perpendicular to the center line, so as to leave a portion around the center line.