The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

A siliconized heterogeneous optical engine. In some embodiments, the siliconized heterogeneous optical engine includes a photonic integrated circuit; an electro-optical chip, on a top surface of the photonic integrated circuit; an electronic integrated circuit, on the top surface of the photonic integrated circuit; an interposer, on the top surface of the photonic integrated circuit; a redistribution layer, on a top surface of the interposer, the redistribution layer including a plurality of conductive traces; and a plurality of protruding conductors, on the conductive traces of the redistribution layer. The electronic integrated circuit may be electrically connected to the electro-optical chip and to a conductive trace of the plurality of conductive traces of the redistribution layer.

A package for integrated circuits includes a base substrate having a mounting face. A first electronic chip has a top face electrically connected to the mounting face and a bottom face mounted to the mounting face by an adhesive layer. A second electronic chip has a bottom face covered with a thermal interface layer and a top face electrically connected to the mounting face. A heat sink includes a first part embedded in the adhesive layer, a second part having a bottom face in contact with the layer of thermal interface material and a top face, and a connection part between the first part and the second part. A coating encapsulates the first and second electronic chips and the heat sink. The top face of the second part of the heat sink exposed from the encapsulating coating.

Provided is a semiconductor device capable of maintaining the flatness of a glass substrate and sufficiently protecting an end portion of the glass substrate. A semiconductor device according to one aspect of the present disclosure includes: a glass substrate including a first surface, a second surface opposite to the first surface, and a first side surface between the first surface and the second surface; wirings provided on the first and second surfaces; a first insulating film that covers the first surface; a second insulating film that covers the second surface; and a third insulating film that covers the first side surface, the third insulating film being continuous with at least one of the first and second insulating films.

Provided herein include various examples of an apparatus, a sensor system and examples of a method for manufacturing aspects of an apparatus, a sensor system. The apparatus may include a die. The apparatus may also include a substrate comprising a cavity. The die may be oriented in a portion of the cavity in the substrate, where the orientation defines a first space in the cavity adjacent to a first edge of the upper surface of the die and a second space in the cavity adjacent to the second edge of the upper surface of the die. The apparatus may further include fluidics fan-out regions comprising a first cured material deposited in the first space and the second space, a surface of the fluidics fan-out regions being contiguous with the upper surface of the die.

Embodiments of the present disclosure are directed to organic spacers for integrated circuits. Among other things, the organic spacers of the embodiments of the present disclosure help provide a cost-efficient and effective solution to address issues such as coefficient of thermal expansion (CTE) mismatches, dynamic warpage, and solder joint reliability (SJR). Other embodiments may be described and claimed.

The third side surface includes inclined surfaces inclined in a direction in which a center in an up-down direction of the third side surface is convex. The mold resin further includes a residual section provided in the center of the third side surface and a dowel section provided between the inclined surface and the residual section. The dowel section projects further in a lateral direction than the inclined surface. The residual section further projects in the lateral direction than the dowel section and has a fracture surface perpendicular to the up-down direction.