An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.

One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing.

One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing.

Shielded radio-frequency (RF) module having reduced area. In some embodiments, an RF module can include a packaging substrate configured to receive a plurality of components, and a plurality of shielding wirebonds implemented on the packaging substrate and configured to provide RF shielding functionality for one or more regions on the packaging substrate. The packaging substrate can include a first area associated with implementation of each shielding wirebond. The RF module can further include one or more devices mounted on the packaging substrate. The packaging substrate can further include a second area associated with mounting of each of the one or more devices. Each device can be mounted with respect to a corresponding shielding wirebond such that the second area associated with the device overlaps at least partially with the first area associated with the corresponding shielding wirebond.

A stack package includes a package substrate having a bond finger and a stack of a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first pad, a second pad, and a first redistributed line connecting the first and second pads to each other. The second semiconductor die includes a third pad, a fourth pad, and a second redistributed line connecting the third and fourth pads to each other. The first and third pads are connected to each other by a first interconnector which is bonded to the bond finger, and the second and fourth pads are connected to each other by a second interconnector.

A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

The present disclosure is directed to a package having a die on a die pad that has a first portion and a second portion, the second portion being larger than the first portion in a first direction. The package includes a plurality of leads, where at least a first lead has a first surface coplanar with a first, lower surface of the first portion of the die pad. The first lead having a second surface that is transverse to the first surface of the first lead. The second surface being an external surface of the lead and package. The second portion of the die pad being an extension that is overlapping the first lead.

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.