A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.

A semiconductor arrangement includes a substrate, a semiconductor element connected to the substrate and including on a side remote from the substrate a contact surface which is connected to the substrate via a first bond connecting means such that as to form on the contact surface a stitch contact arranged between a first loop and a second loop of the first bond connecting means. The first loop has a first maximum and the second loop has a second maximum. A second bond connecting means has a first transverse arranged to run above the first stitch contact and, viewed running parallel to the contact surface, between the first maximum of the first loop and the second maximum of the second loop. The first transverse loop of the second bond connecting means is arranged to run below the first maximum of the first loop and/or the second maximum of the second loop.

Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

A semiconductor device includes a conductivity type drain layer, a conductivity type drift layer, conductivity type base regions located in an upper surface of the drift layer, a conductivity type source region which is disposed inside each of the base regions and is spaced apart from the periphery of the base region, and a channel region is formed between the source region and the periphery of the base region. The semiconductor device further includes a gate insulating layer covering the channel region, a gate electrode which is located on the gate insulating layer and faces the channel region, a plurality of conductivity type column regions, each extends from the plurality of base regions to the drain layer in the drift layer, a trap level forming region in the drift layer, a drain electrode electrically connected to the drain layer, and a source electrode electrically connected to the source region.

An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies.

A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top surface and a bottom surface and including a plurality of pads in the top surface of the substrate; attaching the hermetic module to the bottom surface of the electrode array, the hermetic module having a plurality of bond-pads wherein each bond-pad is adjacent to the bottom surface of the electrode array and aligns with a respective pad; drill holes through each pad to the corresponding bond-pad; filling each hole with biocompatible conductive ink; forming a rivet on the biocompatible conductive ink over each pad; and overmolding the electrode array with a moisture barrier material.

An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies.

Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.

A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads. The bundled memory includes a first memory die and a second memory die side-by-side formed over a substrate, wherein the first memory die includes a first group of pads and the second memory die includes a second group of pads. The encapsulation package material encloses the non-memory chip and the bundled memory, and the non-memory chip is electronically coupling with the bundled memory through the plurality of pads, the first and the second group of pads. The first group of pads corresponds to the second group of pads by rotating a predetermined degree or by mirror mapping.

A semiconductor device includes a conductivity type drain layer, a conductivity type drift layer, conductivity type base regions located in an upper surface of the drift layer, a conductivity type source region which is disposed inside each of the base regions and is spaced apart from the periphery of the base region, and a channel region is formed between the source region and the periphery of the base region. The semiconductor device further includes a gate insulating layer covering the channel region, a gate electrode which is located on the gate insulating layer and faces the channel region, a plurality of conductivity type column regions, each extends from the plurality of base regions to the drain layer in the drift layer, a trap level forming region in the drift layer, a drain electrode electrically connected to the drain layer, and a source electrode electrically connected to the source region.