A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

Described herein are on-chip isolator devices that can be employed in high-power applications and that are designed to enhance high common-mode transient immunity (CMTI) without sacrificing isolator gain. An isolator device includes two dies. A first die supports an isolation barrier and the second die is barrierless. The second die is barrierless in that it lacks isolation materials that are commonly used to sustain isolation barriers in on-chip isolator devices (e.g., polyimide). To enhance CMTI despite the absence of a further isolation barrier formed on the second die, the second die is provided with a tapped impedance element, an impedance element having a tap that couples the impedance element to a reference potential (e.g., to ground). The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die, thus creating a discharge path for common-mode transients.

An electronic component includes at least three terminals extending from a component package. The component includes a depletion-mode III-N transistor, and an enhancement-mode transistor in the package. A gate electrode of the enhancement-mode transistor is electrically connected to the first terminal, a source electrode of the enhancement-mode transistor and a gate electrode of the depletion-mode III-N transistor are electrically connected to the second terminal, a drain electrode of the enhancement-mode transistor is electrically connected to a source electrode of the depletion-mode III-N transistor, and a drain electrode of the depletion-mode III-N transistor is electrically connected to the third terminal. The drain electrode includes multiple drain pads each sequentially a further distance from the third terminal, where a wire-bond extends from each drain pad to the third terminal, each wire-bond having a length, where a diameter of the longest wire-bond is greater than the diameter of the shortest wire-bond.