The instant disclosure provides a method for manufacturing a package structure of a folding magnetic coupling isolator. The method includes providing a leadframe structure including a frame body and a first and a second leadframes connected to the frame body, the first and second leadframes including first and second chip-mounting portions, first and second coil portions, and a plurality of first and second pins and floated pins; disposing the first and second chips on the first and second chip-mounting portions and establishing electrical connections between the first and second chips and the first and second pins; and rotating the first leadframe relative to the frame body and moving the first leadframe to a position above or under the second leadframe, thereby electrically isolating the first leadframe from the second leadframe. The first coil portion and the second coil portion are aligned with and magnetically coupled to each other.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

An example apparatus includes a metal leadframe that includes: first leads in a first portion; second leads in a second portion spaced from the first leads, the second leads isolated from the first leads; an isolation barrier mounted to a board side surface of the first portion of the metal leadframe; a semiconductor die mounted to the isolation barrier, the semiconductor die having a sensor on a device side surface facing the first portion of the leadframe, the semiconductor die cantilevered and having bond pads on the device side surface exposed in the opening in the metal leadframe; electrical connections coupling the bond pads and second leads in the second portion of the metal leadframe; and mold compound covering the semiconductor die, the electrical connections, the isolation barrier and portions of the first leads and the second leads, the mold compound forming a package body.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Example embodiments relate to an electronic package, to an electronic device comprising such a package, and to a lead frame for manufacturing the electronic package. Some examples may particularly relate to electronic packages in which radiofrequency (RF) circuitry is arranged. According to the example embodiments, a width of the clamping portion is substantially larger than the width of the lead end portion, the width of the clamping portion being chosen such that bending of the inner part and/or body part relative to the outer part during the application of the molding compound was substantially prevented thereby having avoided flash and/or bleed of molding compound onto the inner part.

A method of forming a contactless transaction card. The method may include providing a card body, defining a window, and attaching an antenna assembly layer to the card body, where the antenna assembly layer includes an antenna, a set of curable connectors, disposed on a set of end regions of the antenna within the window, and a UV-transparent layer, supporting the antenna. The method may include providing a contactless chip module within the window on a first side of the antenna assembly layer, and directing radiation through the UV-transparent layer, wherein the contactless chip module is electrically connected to the antenna via the curable connectors.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.