A method for fabricating a hermetic electronic package includes providing a package body; hermetically coupling a package base plate to the package body; thermally coupling a substrate to the base plate; thermally mounting a semiconductor device to the substrate; bonding at least one high-current input/output (I/O) terminal to the first metalized region of the substrate by a strap terminal that is an integral high current heatsink terminal. A ceramic seal surrounding the at least one high-current I/O terminal is hermetically bonded to an outer surface of the package body. A metal hermetic seal washer surrounding the at least one high-current I/O terminal is hermetically bonded to the ceramic seal and to a portion of the at least one high-current I/O terminal. A lid is seam welded onto the package body.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

An organic circuit carrier including an organic insulation layer and at least one metallization layer arranged on an upper side, a lower side, or the upper side and the lower side of the organic insulation layer is provided. Side surfaces of the at least one metallization layer are embodied in a convexly curved fashion. A circuit arrangement and a power converter including such an organic circuit carrier are also provided. A vehicle such as an aircraft, including such a power converter, is also provided.

A power semiconductor device includes: a power semiconductor element; a control circuit that controls the power semiconductor element; a control substrate having the control circuit mounted thereon; a lid arranged to overlap with at least a portion of the control substrate in a first direction; and at least one external connection terminal having a first portion connected with the control substrate, a second portion to be connected with an external apparatus, and a third portion located between the first portion and the second portion and fixed to the lid, the first portion being constituted as a press-fit portion.

A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

A semiconductor device improved in deterioration detection accuracy by using an inductance of a bonding wire. The semiconductor device includes a first conductor pattern formed on the insulating substrate, the main current of the semiconductor die device flowing through the first conductor pattern; a second conductor pattern formed on the insulating substrate for sensing the potential of the surface electrode of the semiconductor die device; a first bonding wire for connecting the surface electrode and the first conductor pattern; and a second bonding wire. Further, there is a voltage sensing unit which is connected to the first conductor pattern and the second conductor pattern to sense a potential difference between the first conductor pattern and the second conductor pattern at the time of switching of the semiconductor die device; and a deterioration detection unit for detecting deterioration of the first bonding wire by using the sensed potential difference.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.