A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

A half-bridge module includes a substrate with a base metallization layer divided into a first DC conducting area, a second DC conducting area and an AC conducting area; at least one first power semiconductor switch chip bonded to the first DC conducting area and electrically interconnected with the AC conducting area; at least one second power semiconductor switch chip bonded to the AC conducting area and electrically interconnected with the second DC conducting area; and a coaxial terminal arrangement including at least one inner DC terminal, the at least first outer DC terminal and the at least one second outer DC terminal protrude from the module and are arranged in a row, such that the at least one inner DC terminal is coaxially arranged between the at least one first outer DC terminal and the at least one second outer DC terminal; wherein the at least one inner DC terminal is electrically connected to the second DC conducting area; the at least one first outer DC terminal and the at least one second outer DC terminal are electrically connected to the first DC conducting area; and the at least one first outer DC terminal and the at least one second outer DC terminal are electrically interconnected with an electrically conducting bridging element which is adapted for distributing at least a half of the load current between the at least one first outer DC terminal and the at least one second outer DC terminal.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

A semiconductor arrangement includes a controllable semiconductor element having an active region, and bonding wires arranged in parallel to each other in a first horizontal direction. The active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction. Each bonding wire is electrically and mechanically coupled to the controllable semiconductor element by a first number of bond connections arranged above the active region. A first bond connection of each bonding wire is arranged at a first distance from a first edge of the active region. A second bond connection of each bonding wire is arranged at a second distance from a second edge of the active region opposite the first edge. The first and second distances are both less than the first length divided by twice the first number of bond connections.

RC-IGBT chips and RC-IGBT chips correspond to a pair of adjacent RC-IGBT chips in an X direction between the RC-IGBT chips. The RC-IGBT chips satisfy a first arrangement condition in which the chips are separately arranged without a bonding point region and a bonding point region overlapping each other in a Y direction, and a second arrangement condition in which, in the Y direction, the chips are arranged to partially overlap so that a part of emitter electrodes excluding the bonding point region and the bonding point region overlap. The RC-IGBT chips also satisfy the first and second arrangement conditions described above.

A semiconductor module includes a semiconductor element, a substrate, and a bond connector designed as a gate resistor, shunt, resistor in an RC filter or fuse. The bond connector includes a core made of a first metal material and a jacket which is designed to envelope the core and made from a second metal material that is different from the first metal material, with the first metal material having an electrical conductivity which is lower than an electrical conductivity of the second metal material. At least one of the semiconductor element and the substrate is connected to the bond connector.