A semiconductor device includes a first semiconductor chip including a plurality of first control electrodes, each of which is disposed at a respective one of corner portions on a first front surface thereof, a first output electrode disposed on the first front surface, and a first input electrode disposed on a first rear surface thereof, a second semiconductor chip including a plurality of second control electrodes, each of which is disposed at a respective one of corner portions on a second front surface thereof, a second output electrode disposed on the second front surface, and a second input electrode disposed on a second rear surface thereof, the second semiconductor chip being disposed adjacent to the first semiconductor chip, and a first connection wire which connects one of the first control electrodes and one of the second control electrodes.

A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k−1th semiconductor chip when k is 1.

A semiconductor module, including: plurality of output elements provided to constitute an upper arm and a lower arm; a resin case provided surrounding an accommodation space for accommodating the output elements; an arm-to-arm wiring line for connecting the upper arm with the lower arm; an output terminal, which is connected to the arm-to-arm wiring line and is for outputting output currents from the output elements to a load being external to the semiconductor module; a sense terminal, which is connected to the arm-to-arm wiring line and is for detecting currents that flow in the output elements; and an inductor provided between a connection point for connecting the arm-to-arm wiring line with the output terminal, and the output terminal is provided. An inductance of the inductor is 1 μH or more.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

A semiconductor module includes a laminated substrate including an insulating board and a plurality of circuit boards that are arranged on an upper face of the insulating board, the plurality of circuit boards including first and second circuit boards, a semiconductor element disposed on the first circuit board and including, on an upper face of the semiconductor element, a main electrode, a gate pad, and a gate runner electrically connected to the gate pad, and a first wiring member electrically connecting the main electrode to the second circuit board. The gate runner extends so as to divide the main electrode into a plurality of electrodes including a first main electrode at a first side and a second main electrode at a second side, and the first wiring member is arranged to cross over the gate runner.

A power module includes a substrate that is electrically insulative and includes a substrate main surface and a substrate back surface at opposite sides in a thickness direction. The power module also includes a mounting layer that is conductive and arranged on the substrate main surface. The power module further includes a graphite plate having anisotropic thermal conductivity and including a plate main surface and a plate back surface at opposite sides in the thickness direction. The plate back surface is connected to the mounting layer. The power module further includes a power semiconductor element arranged on the plate main surface.

A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.

A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.

An object is to provide a semiconductor device capable of accurately detecting a temperature of a transistor part and a temperature of the diode part, and improving an overheat protection function. A semiconductor device includes a semiconductor chip having a cell region made up of a plurality of cells including cells corresponding to a transistor part and a diode part, respectively, a temperature detection part detecting a temperature of the transistor part, and a temperature detection part detecting a temperature of the diode part, the temperature detection part is disposed in the cell corresponding to the transistor part, and the temperature detection part is disposed in the cell corresponding to the diode part.