A transistor device includes a semiconductor substrate having a first major surface and transistor cells formed therein. Each transistor cell includes a drift region of a first conductivity type, a body region of an opposing second conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region, a columnar field plate trench extending into the first major surface and including a field plate, and a gate trench structure extending into the first major surface and including a gate electrode. A first metallization structure on the first major surface provides a first contact pad for wire bonding. At least one of depth and doping level of the body region is locally increased within the transistor cells located within one or more first areas of the first major surface. One or more of the first areas are located underneath the first contact pad.

A method of manufacturing a WBGA package includes providing a carrier having a first surface and a second surface opposite to the first surface of the carrier, wherein the carrier has a through hole extending between the first surface and the second surface of the carrier; disposing an electronic component on the second surface of the carrier, wherein the electronic component includes a first bonding pad and a second bonding pad; and electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

A semiconductor device includes: a substrate; a device region provided in the substrate; a terminal covering the device region in a plan view; a plurality of pseudo-bumps densely arranged on the terminal in a state of being opened from a wire; and at least one genuine bump arranged more sparsely than the plurality of the pseudo-bumps on the terminal in a state of being connected to the wire.

Semiconductor module having a first substrate, a second substrate and a spacer distancing the substrates from each other, wherein the spacer is formed by at least one elastic shaped metal body.

It is an object of the present invention to improve a heat radiation property of a metal wire on a semiconductor chip in a power module. A power module includes: a plurality of metal wires connected to a surface of at least one semiconductor chip; and a thermal conductive sheet having contact with the metal wire. The metal wire includes: at least one first metal wire connecting a surface of the semiconductor chip and a circuit pattern and at least one second metal wire connecting two points on the surface of the semiconductor chip and having the same potential as the first metal wire. The thermal conductive sheet includes a graphite sheet, and a sheet surface of the thermal conductive sheet has contact with the at least one first metal wire and the at least one second metal wire.

An insulated substrate (2) includes first and second circuit patterns (5,4). A semiconductor device (7) includes first and second main electrodes (9,8) connected to the first and second circuit patterns (5,4) respectively and through which main currents flow. A first lead (12) is solder jointed to the first circuit pattern (5). A second lead (11) is ultrasonic jointed to the second circuit pattern (4).

A semiconductor device includes: an insulating resin; a metal pattern provided on the insulating resin; a semiconductor chip jointed to the metal pattern; a case bonded on the insulating resin and surrounding the semiconductor chip; a sealing material sealing the semiconductor chip inside the case; and a cover provided on an upper part of the case and covering the semiconductor chip and the sealing material, wherein a groove having a V-shaped cross-section is provided on the cover.

A method of forming a power semiconductor module includes providing a substrate of planar sheet metal, forming channels in an upper surface of the substrate that partially extend through a thickness of the substrate and define a plurality of islands in the substrate, mounting a first semiconductor die on a first one of the islands, forming a molded body of encapsulant that covers the substrate, fills the channels, and encapsulates the semiconductor die, forming a hole in the molded body and a recess in the upper surface of the substrate beneath the hole, and arranging a press-fit connector in the hole and forming a mechanical and electrical connection between an interior end of the press-fit connector and the substrate.

An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.

An object of the present disclosure is to suppress a shrinkage cavity without affecting the layout or the insulation performance of the semiconductor element in a power semiconductor device. A power semiconductor device includes a heat radiation plate; an insulating substrate bonded in a bonding region on an upper surface of the heat radiation plate with a bonding material containing a plurality of elements having different solidification points; a semiconductor element mounted on an upper surface of the insulating substrate; and a bonding wire bonded in the bonding region on the upper surface of the heat radiation plate such that the bonding wire surrounds the semiconductor element in plan view.