A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.

According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Described examples include a microelectronic device with a high voltage capacitor that includes a high voltage node, a low voltage node, a first dielectric disposed between the low voltage node and the high voltage node, a first conductive plate disposed between the first dielectric and the high voltage node, and a second dielectric disposed between the first conductive plate and the high voltage node.

A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material. The integrated circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

A Pd-coated Cu bonding wire of an embodiment contains Pd of 1.0 to 4.0 mass %, and a S group element of 50 mass ppm or less in total (S of 5.0 to 12.0 mass ppm, Se of 5.0 to 20.0 mass ppm, or Te of 15.0 to 50 mass ppm). At a crystal plane of a cross section of the wire, a <100> orientation ratio is 15% or more, and a <111> orientation ratio is 50% or less. When a free air ball is formed on the wire and a tip portion is analyzed, a Pd-concentrated region is observed on the surface thereof.

A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.

A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.

An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.