A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.

The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.

The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.

Damage to a semiconductor device at the time of forming a via hole in which a through electrode is arranged is prevented. The semiconductor device includes a cylindrical insulating film, a front surface side pad, a conductor layer, and a back surface side pad. The cylindrical insulating film is configured in a cylindrical shape penetrating a semiconductor substrate. The front surface side pad is formed adjacent to a front surface of the semiconductor substrate inside the cylindrical insulating film. The conductor layer is arranged adjacent to the front surface side pad and an inner side of the cylindrical insulating film after removing the semiconductor substrate inside the cylindrical insulating film adjacent to the front surface side pad. The back surface side pad is arranged on a back surface of the semiconductor substrate and is connected to the front surface side pad via the conductor layer.

A electronic device includes a substrate, a first metal film, an insulating film, a second metal film, and a third metal film. The substrate has one surface. The first metal film is disposed on the one surface. The insulating film is disposed on the one surface in a state covering the first metal film. The insulating film has a contact hole exposing the first metal film. The second metal film is disposed on a portion of the first metal film exposed from the contact hole and a periphery of the contact hole. The third metal film is made of gold and disposed on the second metal film. The first metal film, the second metal film, and the third metal film are stacked as a pad portion.

A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures. External bonding pads may be subsequently formed.

A substrate largely or entirely devoid of return current vias is disclosed. The substrate may include a first signal layer, a ground plane, a power plane and a second signal layer, each separated by a dielectric material. The ground plane and power plane together form a capacitor providing a return current path for the current in the signal layers.

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.

An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

An inertial sensor according to the present disclosure includes a sensor element having a multilayer structure in which a first substrate, a second substrate, and a sensor substrate are stacked one on top of another. The first substrate includes a substrate body, a first interconnect, an electrode layer, and a silicon member. The first interconnect is provided inside the substrate body. The electrode layer is provided for the substrate body and electrically connected to the first interconnect. The silicon member is provided at an end of the substrate body. The silicon member has, in a cross-sectional view, a curved portion and a linear portion connected to the curved portion. The electrode layer is provided to cover the curved portion and the linear portion.