A semiconductor package includes a semiconductor die having a bond pad, an insulating layer covering the bond pad and having an opening with sidewalls, a polymer layer formed over the insulating layer and covering the sidewalls of the opening in the insulating layer, the polymer layer having an opening, and an electrical conductor having a conductive base attached to a part of the bond pad exposed by the insulating layer opening and the polymer layer opening. The polymer layer includes an upper segment and a lower segment. The polymer layer opening is larger in the upper segment than in the lower segment.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

A redistribution layer for an integrated circuit includes a conductive body in electrical contact with an interconnection layer. The conductive body has a lateral surface and a top surface. A conductive coating layer made of a material that is Palladium or includes Palladium uniformly covers the lateral surface and the top surface of said conductive body and is absent laterally to the conductive body.

A semiconductor device includes an insulating support member, a first and a second conductive layer, a first semiconductor element, a first lead, a first detection conductor and a first gate conductor. The first and second conductive layers are disposed on a front surface of the insulating support member. The first semiconductor includes a first and a second electrode on the same side, and a third electrode disposed on the other side and electrically connected to the first conductive layer. The first lead is connected to the first and second conductive layer. The first detection conductor is connected to the first electrode. The first gate conductor is connected to the second electrode. At least one of the first detection conductor and the first gate conductor has an end connected to the first semiconductor element. The end has a coefficient of linear expansion smaller than that of the first conductive layer.

A semiconductor package includes: a substrate; a plurality of leads; a semiconductor die attached to the substrate at a first side of the semiconductor die, the semiconductor die having a bond pad at a second side of the semiconductor die opposite the first side; and a ball-bond interconnect structure connecting the bond pad to a first lead of the plurality of leads. The ball-bond interconnect structure includes at least two levels of ball-bonded wire loops stacked on one another, and attached to one another at opposite ends of the stacked ball-bonded wire loops such that the at least two levels of stacked ball-bonded wire loops are electrically in parallel. Methods of manufacturing the semiconductor package are also described.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.

A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

An enhanced bond pad configuration for a light emitting diode (LED) chip of a surface mountable package is presented herein. The surface mountable package comprises an LED chip that has been bonded, within a cavity of the surface mountable package, to a lead frame. The LED chip comprises a first metal layer that has been formed on a first gold bond pad that has been formed on a substrate of the LED chip, or a second gold bond pad that has been formed on the substrate and that surrounds a second metal layer that has been formed on the substate. The surface mountable package further comprises a gold wire that has been ball bonded, via a gold ball, onto the first metal layer or the second metal layer to electrically couple the LED chip to the lead frame.

A semiconductor device in a multi-chip package (MCP) includes a controller, at least one non-volatile memory die including an array of non-volatile memory cells and connected to the controller through wire bonding, and at least one volatile memory die including an array of volatile memory cells and connected to the controller through wire bonding. The controller is configured to control operations of the at least one non-volatile memory die and the at least one volatile memory die.