A semiconductor device is provided, which is configured to improve the adhesion between the resin part and the leads without interfering with proper operation of the semiconductor device. The semiconductor device includes a semiconductor element 1, a first lead 2 including a first pad portion 21, a second lead 3 including a second pad portion 31, a conductor member 61, and a resin part 8. The first pad portion 21 has a first-pad obverse surface 21a including a first smooth region 211 to which an element reverse surface 1b is bonded, and a first rough region 212 spaced apart from the semiconductor element 1 as viewed in z direction and has a higher roughness than the first smooth region 211. The second pad portion 31 has a second-pad obverse surface 31a including a second smooth region 311 to which a second bonding portion 612 is bonded, and a second rough region 312 spaced apart from the second bonding portion 612 as viewed in z direction and has a higher roughness than the second smooth region 311.

A leadframe includes a die pad having arranged thereon a first semiconductor die with an electrically conductive ribbon extending on the first semiconductor die. The first semiconductor die lies intermediate the leadframe and the electrically conductive ribbon. A second semiconductor die is mounted on the electrically conductive ribbon to provide, on the same die pad, a stacked arrangement of the second semiconductor die and the first semiconductor die with the at least one electrically conductive ribbon intermediate the first semiconductor die and the second semiconductor die. Package size reduction can thus be achieved without appreciably affecting the assembly flow of the device.

For example, a semiconductor device includes an output electrode to be connected to an inductive load, a ground electrode to be connected to a ground terminal, first and second transistors connected in parallel between the output and ground electrodes, an active clamp circuit connected to the gate of the first transistor, and a gate control circuit to control the gates of the first and second transistors to keep the first and second transistors on in a first operation state and off in a second operation state. After a transition from the first operation state to the second, before the active clamp circuit operates, the gate control circuit short-circuits between the gate and source of the second transistor.

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

A semiconductor unit includes a plurality of semiconductor chips, and an insulated circuit board including an insulating plate having, in a plan view of the semiconductor unit, a rectangular shape surrounded by first and second sides opposite to each other and third and fourth sides perpendicular to the first and second sides and opposite to each other, an output circuit pattern and an input circuit pattern on a front surface of the insulating plate. The output and input circuit patterns each extend from the third side to the fourth side, and disposed in this order side by side in a main current direction that is a direction from the first side toward the second side. The plurality of semiconductor chips are bonded to the input circuit pattern at an area extending from the third side to the fourth side and including a center of the third and fourth sides.

A semiconductor package includes a substrate extending in a first direction and a second direction perpendicular to the first direction, a first semiconductor chip disposed on the substrate, the first semiconductor chip having a stepped portion, a second semiconductor chip disposed on the substrate and horizontally spaced apart from the first semiconductor chip in the first direction, a third semiconductor chip disposed on the second semiconductor chip and a bottom surface of the stepped portion, and an upper adhesive layer disposed between the second semiconductor chip and the third semiconductor chip, the upper adhesive layer contacting a portion of the bottom surface of the stepped portion.

A semiconductor device includes a heatsink, an insulating resin layer on the heatsink, and a metallic plate including a first surface in contact with a first region of the insulating resin layer and a second surface to which a semiconductor chip is adhered. The device further includes a lead terminal connected to the metallic plate; a first mold resin covering a part of the metallic plate and a part of the lead terminal; and a second mold resin covering another part of the metallic plate, the semiconductor chip, and another part of the lead terminal. The first mold resin has a third surface in the same plane as that of the first surface, the third surface extending from an outer peripheral edge of the metallic plate to that of the insulating resin layer or outside thereof in plan view in contact with the second region of the insulating resin layer.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

A semiconductor device of an aspect of the disclosure includes a switching element, a substrate, a front electroconductive layer, first through third terminals and a sealing resin. The first through third terminals project toward the same side from the sealing resin along a first direction crossing the substrate thickness direction. The first through third terminals are spaced apart in a second direction crossing the thickness and first directions. The first terminal is at an outermost side in the second direction among the first through third terminals. The sealing resin has root-side and tip-side parts. The root-side part is between the first and third terminals in the second direction and offset in the first direction toward the switching element side of the first and third terminals. The tip-side part is offset in the first direction toward the tip side of the first and third terminals exposed from the sealing resin.

A semiconductor device includes a semiconductor element, a first conductive member, a second conductive member, a connecting member, and a metal plate. The semiconductor element has an element obverse surface and an element reverse surface that are spaced apart from each other in a thickness direction. An obverse surface electrode is provided on the element obverse surface. The first conductive member faces the element reverse surface and is bonded to the semiconductor element. The first conductive member and the second conductive member are spaced apart from each other. The connecting member electrically connects the obverse surface electrode and the second conductive member. The metal plate is interposed between the obverse surface electrode and the connecting member in the thickness direction. The obverse surface electrode and the metal plate are bonded to each other by solid-phase diffusion.