An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.

A semiconductor package includes: a lower redistribution structure including a lower insulating layer and a lower redistribution layer; a semiconductor chip disposed on the lower redistribution structure; connection conductors connected to the lower redistribution layer; an encapsulant disposed on the connection conductors; and an upper redistribution structure including an upper insulating layer and upper redistribution layers, wherein the upper insulating layer is disposed on the encapsulant, wherein the upper redistribution layers are disposed on the upper insulating layer, wherein the connection conductors and the encapsulant form a first step, wherein the upper redistribution layers include first and second upper redistribution layers, wherein the first upper redistribution layer does not overlap the connection conductors, wherein the second upper redistribution layer overlaps the connection conductors, wherein the first and second upper redistribution layers form a second step with a height substantially equal to or smaller than that of the first step.

A semiconductor package includes: a lower redistribution structure including a lower insulating layer and a lower redistribution layer; a semiconductor chip disposed on the lower redistribution structure; connection conductors connected to the lower redistribution layer; an encapsulant disposed on the connection conductors; and an upper redistribution structure including an upper insulating layer and upper redistribution layers, wherein the upper insulating layer is disposed on the encapsulant, wherein the upper redistribution layers are disposed on the upper insulating layer, wherein the connection conductors and the encapsulant form a first step, wherein the upper redistribution layers include first and second upper redistribution layers, wherein the first upper redistribution layer does not overlap the connection conductors, wherein the second upper redistribution layer overlaps the connection conductors, wherein the first and second upper redistribution layers form a second step with a height substantially equal to or smaller than that of the first step.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.