Provided is an optical subassembly, which is compact, is easy to manufacture, and has satisfactory high-frequency characteristics. The optical subassembly includes: an eyelet including a first surface, a second surface and a plurality of through-holes; a plurality of lead terminals; a relay substrate including a lead connection surface and a first bonding surface and having first and second conductor patterns formed across the lead connection surface and the first bonding surface; a device mounting unit including a second bonding surface having formed thereon third and fourth conductor patterns; and an optical device configured to convert one of an optical signal and the differential electrical signals into the other. The first and second conductor patterns on the first bonding surface are connected to the third and fourth conductor patterns by bonding wires, respectively, and the first and second bonding surfaces have normal directions in the same direction.

Embodiments of a method and a device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and further includes a first amplifier die, a second amplifier die, and a third amplifier die on the mounting surface. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path, the second amplifier die is configured to amplify a second RF signal along a second signal path, and the third amplifier die is configured to amplify a third RF signal along a third signal path. A side of the first amplifier die including a first output terminal faces a side of the second amplifier die including a second output terminal. The second signal path is parallel to the first signal path, and the third signal path is orthogonal to the first and second signal paths.

Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).

Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.

An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion.

A semiconductor device comprises a power device, a sensor which measures a physical state of the power device to transmit a signal according to the physical state, and a main electrode terminal through which a main current of the power device flows. The semiconductor device further comprises a sensor signal terminal connected to the sensor for receiving a signal from the sensor, a driving terminal which receives driving power for driving the power device, and an open bottomed case which houses the power device, the sensor, the main electrode terminal, the sensor signal terminal and the driving terminal. The first and second terminals electrically conduct with each other to form a double structure. Also, the sensor signal terminal and the driving terminal each have a first terminal and a second terminal which are not embedded within the case.

Semiconductor devices include a plurality of gate fingers extending on a wide bandgap semiconductor layer structure. An inter-metal dielectric pattern is formed on the gate fingers, the inter-metal dielectric pattern including a plurality of dielectric fingers that cover the respective gate fingers. A top-side metallization is provided on the inter-metal dielectric pattern and on exposed portions of the upper surface of the wide bandgap semiconductor layer structure. The top-side metallization includes a first conductive diffusion barrier layer on the inter-metal dielectric pattern and on the exposed portions of the upper surface of the wide bandgap semiconductor layer structure, a conductive contact layer on an upper surface of the first conductive diffusion barrier layer, and a grain stop layer buried within the conductive contact layer.

A half bridge power module (1) comprising a substrate (2) comprising an inner load track (11), two intermediate load tracks (12, 14) and two outer load tracks (10,13), wherein an external terminal is mounted on one of the intermediate load tracks (12, 14), an external terminal (3, 4) is mounted on one of the outer load tracks (10, 13) and an external terminal (5) is mounted on the inner load track (11); wherein semiconductor switches (101, 12, 105, 106) are mounted on the outer load tracks (10, 13) and are electrically connected to the intermediate load track (12); and semiconductor switches (103, 104, 107, 108) are mounted on the intermediate load tracks (12, 14) and are electrically connected to the inner load track (11).

An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion.