A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

A semiconductor package includes a lower semiconductor die and an upper semiconductor die which are stacked with an offset in a first direction, wherein the lower semiconductor die includes a plurality of lower pads arranged in a second direction, which is perpendicular to the first direction, and wherein the upper semiconductor die includes a plurality of upper pads arranged in the second direction. The semiconductor package also includes bent wires electrically connecting the lower pads of the lower semiconductor die with the upper pads of the upper semiconductor die in the first direction. The semiconductor package further includes vertical wires such that a vertical wire is disposed on any one of the lower pad and the upper pad for each pair of pads electrically connected by a bent wire.

A method for manufacturing a semiconductor module can prevent performance and reliability degradation of a semiconductor module. The method for manufacturing a semiconductor module includes: arranging an insulating wiring board on a low die; arranging a sintering material at plural locations on the insulating wiring board and arranging a semiconductor chip on each of the plural sintering materials; arranging a structure above protruding portions of the sintering materials protruding from a periphery of each of the plural semiconductor chips; and sintering by pressurizing and heating the plural sintering materials by an upper die through the structure at the protruding portions and through the semiconductor chips at contacting portions in contact with lower surfaces of the semiconductor chips.

The instant disclosure includes a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator and a method for manufacturing the same. The method includes a leadframe providing step, a chip connecting step and a coil alignment step. The leadframe providing step includes providing a first and a second leadframe each including a chip carrying portion, a coil portion, a plurality of pins and floating pins. The chip connecting step includes disposing at least a first chip and at least a second chip onto the corresponding chip carrying portions for electrically connecting the chips to the pins. The coil alignment step includes arranging the first leadframe above or beneath the second leadframe and applying a first and a second magnetic field to the first and the second leadframes respectively for aligning the coil portions, thereby controlling the coupling effect between two coil portions.

A semiconductor device includes a semiconductor element made up of a semiconductor substrate, an element electrode formed on the substrate, and a wiring layer electrically connected to the element electrode. The semiconductor device further includes a lead frame supporting the semiconductor element, a first conductive member electrically connecting the semiconductor element and the lead frame, a second conductive member overlapping with the semiconductor element as seen in plan view, and a sealing resin covering the semiconductor element, a part of the lead frame, and the first and second conductive member. The wiring layer includes a first pad portion and a second pad portion. The second conductive member has a first connecting portion bonded to the first pad portion and a second connecting portion bonded to the second pad portion.

A semiconductor device includes a semiconductor element made up of a semiconductor substrate, an element electrode formed on the substrate, and a wiring layer electrically connected to the element electrode. The semiconductor device further includes a lead frame supporting the semiconductor element, a first conductive member electrically connecting the semiconductor element and the lead frame, a second conductive member overlapping with the semiconductor element as seen in plan view, and a sealing resin covering the semiconductor element, a part of the lead frame, and the first and second conductive member. The wiring layer includes a first pad portion and a second pad portion. The second conductive member has a first connecting portion bonded to the first pad portion and a second connecting portion bonded to the second pad portion.

[Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

A light emitting device includes: a base comprising a first lead, a second lead, and a supporting member; a light emitting element mounted on the first lead; a protection element mounted on the second lead; a wire including a first end and a second end, wherein the first end is connected to an upper surface of the first lead, and the second end is connected to a first terminal electrode of the protection element; a resin frame located on an upper surface of the base, wherein the resin frame covers at least part of the protection element and surrounds the light emitting element and the first end of the wire; a first resin member surrounded by the resin frame and covering the light emitting element and the first end of the wire; and a second resin member covering the resin frame and the first resin member.

A semiconductor package may include a first chip stack, a second chip stack, and a third chip stack. The third chip stack may include third semiconductor chips, the third chip stack coupled to both of the first and second chip stacks.