High-brightness light emitting diode (LED) packages, systems and methods with improved resin filling and high adhesion are provided. In one aspect, a high brightness package for a light emitter (e.g., a LED or LED chip) can include a body and a cavity disposed in the body. The cavity can include at least one cavity wall extending toward an intersection area of the body where the cavity wall intersects a cavity floor. The package can further include at least one electrical element having first and second surfaces, each of the first and second surfaces proximate the intersection area. The first surface can be disposed on a first plane and the second surface can be at least partially disposed on a second plane that is different than the first plane. The body can at least substantially cover the second surface.

Each of a plurality of semiconductor light-emitting element has, on an upper surface thereof that has a quadrilateral shape, a pair of connecting portions having different polarities from each other. The pair of connecting portions are aligned on a diagonal of the quadrilateral shape. The diagonal intersects a row direction along which the semiconductor light-emitting elements within a row are arranged. Connecting portions having identical polarity are positioned on an imaginary line parallel to the row direction. Metal wires intersect two sides extending from a corner, on the diagonal, of the upper surface of each of the semiconductor light-emitting elements when viewed from a direction perpendicular to a mounting surface of a substrate for mounting the semiconductor light-emitting elements.

A semiconductor device (100) comprising a leadframe with a pad (101) and elongated leads (103) made of a base metal plated with a layer enabling metal-to-metal bonding; a semiconductor chip (110) attached to the pad, the chip having terminals. A metallic wire connection (130) from a terminal to a respective lead, the connection including a first ball bond by a first squashed ball (131) attached to the terminal, and a first stitch bond (132) attached to the lead. A second squashed ball (150) of the wire metal attached to the lead as a second ball bond adjacent to the first stitch bond (132). A package (170) of a polymeric compound encapsulating the chip, wire connection, second ball and at least a portion of the elongated lead, the compound adhering to the materials of the encapsulated entities.

A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.

A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.

Integrated circuit packages with enhanced thermal characteristics are provided. For example, in embodiments, a QFN (quad flat no lead) package includes a die pad that extends to at least one pinless edge of the QFN package body. A portion of the die pad further extends towards a top surface of the QFN package body. By doing so, a low impedance thermal path from a die included in the QFN package to the top of the QFN package body is formed, which causes heat generated by the die to dissipate from one or more sides and the top of the QFN package, and ultimately to the surrounding environment. Furthermore, the path travelled by the heat in a circuit board coupled to the QFN package is shortened, thereby protecting electrical components coupled thereto.

A semiconductor package is provided. The semiconductor package comprises a package substrate including first and second surfaces opposite to each other in a first direction, a plurality of substrate pads on the second surface, and first and second substrate edges respectively extending in a second direction intersecting the first direction and spaced apart from each other in a third direction intersecting the first and second directions, a first semiconductor chip on the package substrate, including third and fourth surfaces opposite to each other in the first direction, a plurality of chip pads and a plurality of chip dummy pad groups on the fourth surface, and first and second chip edges respectively extending in the second direction and spaced apart from each other in the third direction, and a plurality of first wires, each first wire of the plurality of first wires respectively connecting a respective substrate pad of the plurality of substrate pads with the plurality of chip pads, wherein the first chip edge is disposed to be closer to the first substrate edge than the second substrate edge, the plurality of substrate pads is disposed along the first substrate edge, the plurality of chip pads is disposed along the first chip edge, the first semiconductor chip includes third and fourth chip edges respectively extending in the third direction and spaced apart from each other in the second direction, a first corner formed at the intersection of the first chip edge and the third chip edge, a second corner formed at the intersection of first chip edge and the fourth chip edge, a third corner formed at the intersection of the second chip edge and the fourth chip edge, and a fourth corner formed at the intersection of the second chip edge and the third chip edge, and the plurality of chip dummy pad groups is respectively disposed on at least one of the first to fourth corners.