A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess.

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is provided. The method includes the following operations. In a first semiconductor structure, a first bonding layer is formed having a first dielectric layer and a plurality of protruding contact structures. In a second semiconductor structure, a second bonding layer is formed having a second dielectric layer and a plurality of recess contact structures. The plurality of protruding contact structures are bonded with the plurality of recess contact structures such that each of the plurality of protruding contacts is in contact with a respective recess contact structure.

A semiconductor memory device includes a first chip having a peripheral transistor and a first insulating layer, and includes a second chip having a stacked structure and a second insulating layer. The stacked structure includes conductive patterns and insulating patterns alternately stacked with each other, the first insulating layer includes a first bonding surface, the second insulating layer includes a second bonding surface contacting the first bonding surface, and the second chip further includes a protrusion protruding from the second bonding surface of the second insulating layer toward the first insulating layer.

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

A semiconductor device having a three-dimensional structure includes a first wafer including a first bonding pad on one surface thereof; a second wafer including a second bonding pad, which is bonded to the first bonding pad, on one surface thereof bonded to the one surface of the first wafer; a plurality of anti-warpage grooves on the one surface of the first wafer, and laid out in a stripe shape; and a plurality of anti-warpage ribs on the one surface of the second wafer and coupled respectively to the plurality of anti-warpage grooves, and laid out in a stripe shape.

A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.

A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.