A method for digital direct recording of an artwork representing electric connections of components on a substrate includes receiving data representing the artwork, analyzing the artwork representation to identify sections that are similar and sections that are unique and to identify locations of the components in the artwork, and dividing the artwork into modules corresponding to the identified sections, providing a set of unique modules and a set of redundant modules. The method also includes rasterizing each unique module to provide rasterized modules, dividing the rasterized modules into submodules, and receiving measurements representing positions of the components on the substrate. The method also includes receiving measurements representing the position of the substrate, calculating the differences between the measured positions of the components and the artwork positions of the components, calculating modifications for each of the sub modules to compensate for the differences, and recording the modified submodules onto the substrate to form a modified artwork on the substrate.

A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

A method of forming an integrated module forms a surface protrusion structure and a first electrical pad on a first semiconductor substrate and forms a surface indentation structure and a second electrical pad on a second semiconductor substrate. The first semiconductor substrate is disposed over the second semiconductor substrate by substantially matching the protrusion structure to the indentation structure. The first electrical pad is aligned to the second electrical pad to form bonding between the first semiconductor substrate and the second semiconductor substrate.

A chip on glass package assembly includes a glass substrate, a first type chip, a second type chip and a plurality of connecting lines. The glass substrate includes an active area and a peripheral area connected to the active area. The first type chip is mounted on the peripheral area and including a processor. The second type chip is mounted on the peripheral area and located on a side of the first type chip, wherein the second type chip is different from the first type chip. The connecting lines are disposed on the peripheral area and connecting the first type chip and the second type chip.

A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap. Accordingly, after the first and second semiconductor structures are bonded together, at least 99.5% of the active photodetector are electrically connected with their respective RICPs.

Provided is a semiconductor device including an asymmetric electrode arrangement in which a plurality of electrodes are arranged asymmetrically in a vertical or horizontal direction.