Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.

Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

A printed circuit board includes a first insulating layer; an external connection pad embedded in a first surface of the first insulating layer and having a first externally exposed surface disposed at substantially the same level as the first surface of the first insulating layer; a second insulating layer disposed on a second surface of the first insulating layer and having a first surface in contact with the second surface of the first insulating layer; and a first wiring pattern embedded in the second insulating layer and exposed from the first surface of the second insulating layer to be in contact with a second externally exposed surface of the external connection pad opposing the first externally exposed surface.

A method of manufacturing an electronic package structure is disclosed. A solder mask layer is formed on an upper surface of a substrate. A recessed area is formed in the solder mask layer. An electronic component is mounted on the substrate. Pads are disposed on the upper surface of the substrate. The pads respectively correspond to the bumps on a first surface of the electronic component. The pads are electrically connected to the bumps. A heat treatment is performed to make the first surface close to the substrate and form a cavity in the recessed area. The cavity is between the first surface of the electronic component, the solder mask layer and the upper surface of the substrate.

A method for manufacturing a semiconductor apparatus, including preparing a first substrate provided with a pad optionally having a plug and a second substrate or device provided with a plug, forming a solder ball on at least one of the pad or plug of first substrate and the plug of second substrate or device, covering at least one of a pad-forming surface of first substrate and a plug-forming surface of second substrate or device with a photosensitive insulating layer, forming an opening on the pad or plug of the substrate or device that has been covered with photosensitive insulating layer by lithography, pressure-bonding the second substrate or device's plug to the pad or plug of first substrate with the solder ball through the opening, electrically connecting pad or plug of first substrate to second substrate or device's plug by baking, and curing photosensitive insulating layer by baking.

A light emitting diode module includes a substrate, a first soldering section, a second soldering section, a block and a light emitting diode die. The substrate has a top surface and includes a circuit structure. The block is formed on the top surface. The soldering section and the second solder section are formed on the top surface of the substrate and electrically connected with the circuit structure. The block is positioned between the first soldering section and the second solder section. A height of the block is larger than thicknesses of the first soldering section and the second soldering section. The light emitting diode die includes a first electrode and a second electrode being respectively electrically connected to the first soldering section and the second soldering section. The block is positioned between the first soldering section and the second soldering section.

An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component.

A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.

Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also include transferring the light-emitting units to a transfer head. The methods further include attaching at least one of the plurality of light-emitting units on the transfer head to the substrate by a bonding process, wherein the transfer head and the substrate satisfy the following equation during the bonding process:

[00001]$0\leqq .Math.{\int }_{T1}^{T2}A\left(T\right)\mathrm{dT}-{\int }_{T1}^{T3}E\left(T\right)\mathrm{dT}.Math.<0.01$ wherein A(T) is the coefficient of thermal expansion of the transfer head, E(T) is the coefficient of thermal expansion of the substrate, T1 is room temperature, T2 is the temperature of the transfer head, and T3 is the temperature of the substrate.

A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.