A mixed-orientation multi-die (MOMD) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base. MOMD packages may provide a reduced lateral footprint and increased die integration per unit area, as compared with conventional multi-die packages.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also include transferring the light-emitting units to a transfer head. The methods further include attaching at least one of the plurality of light-emitting units on the transfer head to the substrate by a bonding process, wherein the transfer head and the substrate satisfy the following equation during the bonding process:

Q|.sub.T1.sup.T2A(T)dT.sub.T1.sup.T3E(T)dT|<0.01, wherein A(T) is the coefficient of thermal expansion of the transfer head, E(T) is the coefficient of thermal expansion of the substrate, T1 is room temperature, T2 is the temperature of the transfer head, and T3 is the temperature of the substrate.

A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The semiconductor device is disposed on the substrate. The semiconductor device includes a first lateral surface. The underfill is disposed between the substrate and the semiconductor device. The underfill includes a first lateral surface. The first lateral surface of the underfill and the first lateral surface of the semiconductor device are substantially coplanar.

There are provided a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device includes: a first substrate including a peripheral circuit, first conductive contact patterns connected to the peripheral circuit, and a first upper insulating layer having grooves exposing the first conductive contact patterns; a second substrate including a memory cell array, a second upper insulating layer disposed on the memory cell array, the second upper insulating layer formed between the memory cell array and the first upper insulating layer, a second conductive contact patterns protruding through the second upper insulating layer into an opening of the grooves; and conductive adhesive patterns filling the grooves to connect the second conductive contact patterns to the first conductive contact patterns.

An example of a printed structure comprises a target substrate and a structure protruding from a surface of the target substrate. A component comprising a component substrate separate and independent from the target substrate is disposed in alignment with the structure on the surface of the target substrate within 1 micron of the structure. An example method of making a printed structure comprises providing the target substrate with the structure protruding from the target substrate, a transfer element, and a component adhered to the transfer element. The component comprises a component substrate separate and independent from the target substrate. The transfer element and adhered component move vertically toward the surface of the target substrate and horizontally towards the structure until the component physically contacts the structure or is adhered to the surface of the target substrate. The transfer element is separated from the component.

A manufacturing method of an array substrate includes forming a plurality of bonding pads in a bonding region of a base substrate, and forming at least one insulating support part at at least one position where the plurality of bonding pads are not provided in the bonding region of the base substrate.

In a described example, a packaged device includes a substrate having a device mounting surface with conductive lands having a first thickness spaced from one another on the device mounting surface. A first polymer layer is disposed on the device mounting surface between the conductive lands having a second thickness equal to the first thickness. The conductive lands have an outer surface not covered by the first polymer layer. A second polymer layer is disposed on the first polymer layer, the outer surface of the conductive lands not covered by the second polymer layer. Conductive nanoparticle material is disposed on the outer surface of the conductive lands. A third polymer layer is disposed on the second polymer layer between the conductive nanoparticle material on the conductive lands. At least one semiconductor device die is mounted to the third polymer layer having electrical terminals bonded to the conductive nanoparticle material.

The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.