An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.

An encapsulation of laser direct structuring (LDS) material is molded onto first and second semiconductor dice. A die-to-die coupling formation between the first and second semiconductor dice includes die vias extending through the LDS material to reach the first and second semiconductor dice and a die-to-die line extending at a surface of the encapsulation between the die vias. After laser activating and structuring selected locations of the surface of the encapsulation for the die vias and die-to-die line, the locations are placed into contact with an electrode that provides an electrically conductive path. Metal material is electrolytically grown onto the locations of the encapsulation by exposure to an electrolyte carrying metal cations. The metal cations are reduced to metal material via a current flowing through the electrically conductive path provided via the electrode. The electrode is then disengaged from contact with the locations having metal material electrolytically grown thereon.

An encapsulation of laser direct structuring (LDS) material is molded onto a substrate having first and second semiconductor dice arranged thereon. Laser beam energy is applied to a surface of the encapsulation of LDS material to structure therein die vias extending through the LDS material to the first and second semiconductor dice and a die-to-die line extending at surface of the LDS material between die vias. Laser-induced forward transfer (LIFT) processing is applied to transfer electrically conductive material to the die vias and the die-to-die line extending between die vias. A layer of electrically conductive material electroless grown onto the die vias and the die-to-die line facilitates improved adhesion of the electrically conductive material transferred via LIFT processing.

A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.

A semiconductor device, such as a QFN (Quad-Flat No-lead) package, includes an insulating encapsulation of a semiconductor chip. The insulating encapsulation is formed by a first encapsulation material which encapsulates the semiconductor chip and a second encapsulation material that is molded onto an upper surface of the first encapsulation material. The first encapsulation material includes an oblique cavity extending from the upper surface. The second encapsulation material includes an anchoring protrusion that enters into the cavity.

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component including a terminal made of a first electrically conductive material and being embedded in the stack, a recess in the stack exposing at least a part of the terminal, an interface structure on the at least partially exposed terminal and an electrically conductive structure on the interface structure made of a second electrically conductive material.

A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

A manufacturing method of a semiconductor package includes disposing one or more semiconductor devices on a base substrate, each of the one or more semiconductor devices having an external terminal; forming a frame on the base substrate, the frame surrounding the one or more semiconductor devices; and forming a resin insulating layer inside the frame, the resin insulating layer sealing the one or more semiconductor devices and the resin insulating layer including a resin insulating material; wherein a surface of each of the one or more semiconductor devices on which the external terminal is not provided faces the base substrate.

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.