Patent classifications
H01L2224/85045
COATED WIRE
A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core itself consists of: (a) pure silver consisting of (a1) silver in an amount in the range of from 99.99 to 100 wt.-% and (a2) further components in a total amount of from 0 to 100 wt.-ppm or (b) doped silver consisting of (b1) silver in an amount in the range of from >99.49 to 99.997 wt.-%, (b2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm and (b3) further components in a total amount of from 0 to 100 wt.-ppm, or (c) a silver alloy consisting of (c1) silver in an amount in the range of from 89.99 to 99.5 wt.-%, (c2) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (c3) further components in a total amount of from 0 to 100 wt.-ppm, or (d) a doped silver alloy consisting of (d1) silver in an amount in the range of from >89.49 to 99.497 wt.-%, (d2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm, (d3) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (d4) further components in a total amount of from 0 to 100 wt.-ppm, wherein the at least one doping element (d2) is other than the at least one alloying element (d3), wherein the individual amount of any further component is less than 30 wt.-ppm, wherein the individual amount of any doping element is at least 30 wt.-ppm, wherein all amounts in wt.-% and wt.-ppm are based on the total weight of the core, and wherein the coating layer is a double-layer comprised of a 1 to 1000 nm inner layer of gold and an adjacent 0.5 to 100 nm thick outer layer of palladium or a double-layer comprised of a 0.5 to 100 nm thick inner layer of palladium and an adjacent >200 to 1000 nm thick outer layer of gold.
SEMICONDUCTOR PACKAGE WITH ISOLATED HEAT SPREADER
A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.
PACKAGE WITH SHIFTED LEAD NECK
A semiconductor package includes a pad and leads having a planar profile shaped from a planar base metal, a semiconductor die attached to the pad, a wire bond extending from the semiconductor die to a respective lead, and mold compound covering the semiconductor die, the wire bond, and a first portion of the respective lead, wherein a second portion of the respective lead extends beyond the mold compound. A shape of the respective lead within the planar profile includes a notch indented relative to a first elongated side of the shape of the respective lead and a protrusion protruding outwardly relative to a second elongated side of the shape of the respective lead. The notch and the protrusion are each partially covered by the mold compound and partially outside the mold compound.
SEMICONDUCTOR PACKAGE SUBSTRATE WITH A SMOOTH GROOVE ABOUT A PERIMETER OF A SEMICONDUCTOR DIE
A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.
Wire bonding method and wire bonding apparatus
A wire bonding method comprises: preparing a wire bonding apparatus; a step of forming a free air ball; a first height measuring step of measuring the height of a first electrode by detecting whether the free air ball is grounded to the first electrode; a second height measuring step of measuring the height of a second electrode by detecting whether the free air ball is grounded to the second electrode; a first bonding step of controlling the height of a bonding tool based on the measurement result in the first height measuring step, and bonding the free air ball to the first electrode; and a second bonding step of controlling the height of the bonding tool based on the measurement result in the second height measuring step, and bonding a wire to the second electrode to connect the first and the second electrodes. Thus, electrodes can be correctly bonded.
CUPD WIRE BOND CAPILLARY DESIGN
A capillary for performing ball bonding includes a body defining a lumen, a first blade defined in a lower tip of the body, and a second blade defined in the lower tip of the body for increasing reliability of a ball bonding procedure performed using the capillary.
Coated wire
A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core includes: (a) pure silver consisting of silver and further components; or (b) doped silver consisting of silver, at least one doping element, and further components; or (c) a silver alloy consisting of silver, palladium and further components; or (d) a silver alloy consisting of silver, palladium, gold, and further components; or (e) a doped silver alloy consisting of silver, palladium, gold, at least one doping element, and further components, wherein the individual amount of any further component is less than 30 wt.-ppm and the individual amount of any doping element is at least 30 wt.-ppm, and the coating layer is a single-layer of gold or palladium or a double-layer comprised of an inner layer of nickel or palladium and an adjacent outer layer of gold.
Wire bonding apparatus, circuit for wire bonding apparatus, and method for manufacturing semiconductor device
The present invention comprises: a spool (10); a clamper (22); a torch electrode (31); a high-voltage power source circuit (30); a non-bonding detection circuit (40); a first changeover switch (50) switching a connection between the spool (10) and the high-voltage power source circuit (30) or the non-bonding detection circuit (40); and a relay (53) turning on/off a connection between the clamper (22) and a spool side of the first changeover switch (50), and comprises a control part (60) that sets the first changeover switch (50) to the high-voltage power source circuit side and turns off the relay (53) to generate electric discharge, and that sets the first changeover switch (50) to the non-bonding detection circuit side and turns on the relay (53) to perform non-bonding detection. Due to this configuration, electric corrosion of a wire clamper can be suppressed and non-bonding detection can be carried out with a simple configuration.
CHIP PACKAGE STRUCTURE AND ELECTRONIC DEVICE
A chip package structure and an electronic equipment may reduce probability of short circuit failure during chip packaging and improve chip reliability. The chip package structure includes: a chip, a substrate, and a lead; the chip is disposed above the substrate; wherein the chip includes a pin pad and a test metal key, and the lead is configured to electrically connect the pin pad and the substrate; the test metal key is disposed in an edge region of the chip that is not under the lead.
WIRE BONDING APPARATUS
To provide a wire bonding apparatus, which is insusceptible to a bonding state at a second bonding point due to a wire cut error or the like, or to members such as a capillary and a wire, and is capable of automatically protruding the wire from a leading end of the capillary, provided is a wire bonding apparatus including: a capillary (6) having a through hole through which a wire (40) is to be inserted; a holding unit, which is provided above the capillary (6), and is configured to hold the wire (40) inserted through the capillary (6); and a vibrating unit configured to vertically vibrate the capillary (6). Under a state in which the holding unit holds the wire (40), the vibrating unit vertically vibrates the capillary (6) so that the wire (40) is protruded from the leading end of the capillary.