A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A wire bonding apparatus includes: a capillary, performing predetermined processing on a workpiece and movable with respect to the workpiece; an optical mechanism, moving together with the capillary; and a controller. The optical mechanism includes: a first imaging unit, acquiring a first image obtained by imaging a standard point set within an imaging range; and a second imaging unit, acquiring a second image obtained by imaging a reference point formed at a predetermined distance from the capillary. The controller positions the capillary with respect to the workpiece based on the first image, and calculates a positioning correction amount of the capillary based on the second image.

A semiconductor package may include a package substrate; a lower chip stack sequentially stacked on the package substrate and including first semiconductor chips and second semiconductor chips; a first double die chip provided on the lower chip stack and including a first sub chip stacked on the first semiconductor chips, a second sub chip stacked on the second semiconductor chips, and a first connection portion; an upper chip stack sequentially stacked on the first double die chip and including third semiconductor chips sequentially stacked on the first sub chip and fourth semiconductor chips sequentially stacked on the second sub chip; a second double die chip provided on the upper chip stack and including a third sub chip stacked on the fourth semiconductor chips, a fourth sub chip stacked on the third semiconductor chips, and a second connection portion.

Provided is a semiconductor package including a chip stack that includes first and second semiconductor chips stacked in a first direction and offset in a second direction intersecting the first direction, each of the first and second semiconductor chips comprising chip pads in the second direction, a redistribution substrate on the chip stack, first bonding wires connecting the redistribution substrate and the chip pads of the first semiconductor chip, and first vertical wires connecting the redistribution substrate and the chip pads of the second semiconductor chip. Each of the first bonding wires includes a first portion in contact with one of the chip pads of the first semiconductor chip and having a first width, and a second portion extending perpendicularly on the first portion and having a second width, each of the first vertical wires has a third width, and each of the second and third widths is smaller than the first width.