Patent classifications
H01L2224/85207
PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes a first surface, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a first magnetic field shielding, including a first portion proximal to the third surface of the semiconductor chip, wherein the first portion has a first height calculated from the mounting surface to a top surface, and a second portion distal to the semiconductor chip, has a second height calculated from the mounting surface to a position at a surface facing away from the mounting surface, wherein the second height is less than the first height, wherein the second portion has an inclined sidewall.
Power amplifier systems with control interface and bias circuit
One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component, and a bias circuit. The power amplifier and the passive component can be on a first die. The bias circuit can be on a second die. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.
Power amplifier systems with control interface and bias circuit
One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component, and a bias circuit. The power amplifier and the passive component can be on a first die. The bias circuit can be on a second die. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.
TEMPORARY PROTECTIVE FILM, REEL BODY, PACKAGING BODY, PACKAGE BODY, TEMPORARY PROTECTIVE BODY, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
A temporary protective film including a support film and an adhesive layer provided on one surface or both surfaces of the support film. The support film is a polyimide film. The thickness of the adhesive layer is less than 8 μm.
SOLID-STATE IMAGING DEVICE
Provided is a solid-state imaging device that suppresses propagation of a crack. There is provided a solid-state imaging device including: a first substrate on which a pixel unit configured to perform photoelectric conversion is formed; and a second substrate on which a logic circuit configured to process a pixel signal outputted from the pixel unit is formed, in which the first and second substrates are laminated by being connected by metal binding between wiring layers that are formed individually, an opening hole is formed on an outer periphery of the pixel unit to penetrate the first and second substrates to reach an upper part of a wire bonding pad formed in the second substrate, the second substrate includes an insulating layer below the wire bonding pad, and the insulating layer includes a first insulating film.
SEMICONDUCTOR PACKAGE INCLUDING PROCESSOR CHIP AND MEMORY CHIP
A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.
Semiconductor device having an electrical connection between semiconductor chips established by wire bonding, and method for manufacturing the same
A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball.
Package structure and method for fabricating the same
The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes: a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a magnetic device disposed in the semiconductor chip, a first magnetic field shielding at least partially surrounding the third surface, a second magnetic field shielding, including a top surface facing the second surface of the semiconductor chip, and a molding surrounding the semiconductor chip, wherein the entire top surface of the second magnetic field shielding is in direct contact with the molding.
Package structure and method for fabricating the same
The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes: a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a magnetic device disposed in the semiconductor chip, a first magnetic field shielding at least partially surrounding the third surface, a second magnetic field shielding, including a top surface facing the second surface of the semiconductor chip, and a molding surrounding the semiconductor chip, wherein the entire top surface of the second magnetic field shielding is in direct contact with the molding.
Wire bonding method and wire bonding device
A wire bonding method includes bringing a capillary and a wire inserted through the capillary into pressure contact with a bonding point of a lead placed on an XY stage to bond the wire to the lead, including moving the XY stage in a state in which the capillary is in pressure contact with the lead to move the capillary along a movement locus including a plurality of arc portions.