Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

A semiconductor device includes a first semiconductor wafer, a second semiconductor wafer, and a first conductive via. The first semiconductor wafer includes a first substrate and at least one first conductive layer disposed on a top surface of the first substrate. The second semiconductor wafer is disposed on the first semiconductor wafer. The second semiconductor wafer includes a second substrate and a first conductive pad disposed on a top surface of the second substrate. The first conductive via extends from the first conductive pad to the first conductive layer.

A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.

An exemplary assembly includes a top circuit substrate; a bottom circuit assembly that underlays the top circuit substrate and is attached to the top circuit substrate by an adhesive layer as a stiffener, the adhesive layer, and a plurality of conductive balls. The top circuit substrate includes a plurality of upper vias that extend through the top circuit substrate. The bottom circuit assembly includes a plurality of lower vias that extend through the bottom circuit assembly. The adhesive layer includes internal connections that electrically connect the upper vias to the lower vias. The conductive balls are housed in the lower vias. The bottom circuit assembly has an elastic modulus at least six times the elastic modulus of the top circuit substrate, and has a coefficient of thermal expansion at least two times the coefficient of thermal expansion of the top circuit substrate.

Flexible devices including conductive traces with enhanced stretchability, and methods of making and using the same are provided. The circuit die is disposed on a flexible substrate. Electrically conductive traces are formed in channels on the flexible substrate to electrically contact with contact pads of the circuit die. A first polymer liquid flows in the channels to cover a free surface of the traces. The circuit die can also be surrounded by a curing product of a second polymer liquid.

Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

The present disclosure provides a microcontroller unit and its fabrication method. The microcontroller unit includes a logic control substrate, and also includes at least one memory die and at least one non-memory die, which are disposed on the logic control substrate. The logic control substrate includes a semiconductor device layer and an interconnection dielectric layer. A central processing unit and at least one logic controller are formed in the semiconductor device layer. All memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another, and the at least one memory die is electrically connected to the central processing unit through a corresponding electrical interconnection structure in the interconnection dielectric layer. All non-memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another and are electrically connected to corresponding logic controllers through corresponding electrical interconnection structures in the interconnection dielectric layer.

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer. The redistribution structure is disposed on a second side of the first semiconductor die opposing to the first side, and the redistribution structure is electrically coupled to the first semiconductor die and the first conductive layer of the electromagnetic shielding structure.