An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.

An electronic-component-embedded substrate includes a base having flexibility and cavities formed therethrough, electronic components disposed in the cavities, respectively, and interconnects disposed on the base and connected to the electronic components, wherein the interconnects include a metal foil having openings that abut the electronic components, and include a plating layer disposed on the metal foil and connected to the electronic components through the openings.

The present disclosure provides a chip packaging structure and method, using a back-to-back packaging structure, and realizing electrical connection between chips through TSV holes or cooperation between TSV and TMV holes, completely penetrating two chips. Thus, the TSV hole passing through a silicon material may not need to be formed in advance on the chips before bonding the chips, thereby the requirement of alignment accuracy of the chips can be reduced, and the process difficulty can be reduced. In addition, as the back-to-back packaging process is adopted, the heat dissipation efficiency of the chips can be improved, and the problem of circuit breakage due to materials with different expansion coefficients present between the chips can be avoided.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

Provided are a chip fine line fan-out package structure and a manufacturing method therefor. The chip fine line fan-out package structure provided and the chip fine line fan-out package structure manufactured using the manufacturing method each include an inter-chip fine winding layer and a package winding layer. The line width and line spacing of the inter-chip fine winding layer are less than the line width and line spacing of the package winding layer, and therefore, a user can choose to use different package winding layers according to actual needs. Therefore, the chip fine line fan-out package structure and the package structure manufactured using the manufacturing method can meet the use demands of users in more scenarios.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

A display device includes a substrate including a display area and a non-display area, and a first surface and a second surface; pixels disposed on the first surface; a signal line disposed on the first surface, and electrically connected to each pixel; a cushion layer disposed on the pixels and the signal line, and including at least one contact hole that exposes a portion of the signal line; a connector disposed in the at least one contact hole and electrically connected to the signal line; and a driver disposed on the cushion layer and electrically connected to the pixels through the connector. Each pixel includes a display element layer disposed on the first surface and including at least one light emitting element, and a pixel circuit layer disposed on the display element layer and including at least one transistor electrically connected to the at least one light emitting element.

An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.

Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

A manufacturing method for a semiconductor apparatus sequentially includes bonding a first chip and a second chip together using an adhesive. The first chip includes a first electrode and has a protrusion, and the second chip has a recess. In the bonding, the first chip and the second chip are bonded together in such a manner that the protrusion is positioned into the recess. Further, the method includes forming a through hole in the second chip to expose the first electrode, the first surface being opposite to a second surface having the recess, and forming the second electrode which is electrically connected to the first electrode, in the through hole.