A semiconductor device is disclosed including one or more semiconductor dies mounted on substrate. Each semiconductor die may be formed with a ferromagnetic layer on a lower, inactive surface of the semiconductor die. The ferromagnetic layer pulls the semiconductor dies down against each other and the substrate during fabrication to prevent warping of the dies. The ferromagnetic layer also balances out a mismatch of coefficients of thermal expansion between layers of the dies, thus further preventing warping of the dies.

A semiconductor package includes first bump structures that include a stud portion disposed below the second rear surface pads of the first group, and a bonding wire portion that extends from the stud portion and is connected to the first front surface pads of the first group; second bump structures disposed below the second rear surface pads of the second group; an encapsulant that encapsulates the second semiconductor chip and the first and second bump structures; and a redistribution structure disposed below the encapsulant, and that includes an insulating layer, redistribution layers disposed below the insulating layer, and redistribution vias that penetrate through the insulating layer and connect the redistribution layers to the first bump structures or the second bump structures. At least a portion of the redistribution vias connected to the first bump structures is in contact with the stud portion.

A method of manufacturing a WBGA package includes providing a carrier having a first surface and a second surface opposite to the first surface of the carrier, wherein the carrier has a through hole extending between the first surface and the second surface of the carrier; disposing an electronic component on the second surface of the carrier, wherein the electronic component includes a first bonding pad and a second bonding pad; and electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface; forming an opening extending between the upper surface and the lower surface of the substrate; attaching a first electronic component to the upper surface of the substrate, wherein an active surface of the first electronic component faces the upper surface of the substrate; attaching a second electronic component to the first electronic component, wherein an active surface of the second electronic component faces the upper surface of the substrate; and forming a bonding wire on the substrate, wherein the bonding wire passes through the opening of the substrate and electrically connects the substrate and one of the first electronic component or the second electronic component.

Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.

A step-type stacked chip packaging structure based on a resin spacer that includes: a plastic packaging material, a circuit board, a resin spacer, a first chip, a second chip and an electrical connection assembly. The resin spacer, the first chip, and the second chip are stacked on the circuit board respectively. The second chip is stacked on the first chip in a stepped manner. The circuit board, the first chip and the second chip are electrically connected together through the electrical connection assembly. The resin spacer uses a fiber glass fabric as its base material, a weight percent of the fiber glass fabric is 10-60 wt %, and the following components are attached to the fiber glass fabric as a percentage by the total weight of the resin spacer: 8-40 wt % of epoxy resin, 10-30 wt % of quartz powder, 2-10 wt % of aluminum oxide, 1-8 wt % of calcium oxide, and 1-8 wt % of curing agent.

A semiconductor chip including a main electrode and a control electrode is bonded to a substrate. A wiring chip including a first electrode, a second electrode and a wiring is bonded to the substrate. A main electrode member is bonded to the main electrode. A control electrode member is bonded to the second electrode. The control electrode is bonded to the first electrode with a connection member. The semiconductor chip, the substrate, the wiring chip, the main electrode member, the control electrode member and the connection member are putted into a mold and are sealed with sealing material by injecting the sealing material into the mold in a state that distal end surfaces of the main electrode member and the control electrode member are pressed against a buffer material provided between the main electrode member/the control electrode member and the mold. The sealing material is not ground.

An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.